中国科学院计算技术研究所机构知识库

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限定条件	作者：Chen, Shuai    第一作者

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 页码: 14 作者:  Cao, Yuan;  Liu, Wanyi;  Zheng, Yue;  Chen, Shuai;  Ye, Jing;  Qian, Lei;  Chang, Chip-Hong 收藏  |  浏览/下载：8/0  |  提交时间：2023/12/04 Entropy  Authentication  System-on-chip  Protocols  Jitter  Computer architecture  Rail to rail outputs  True random number generator  physical unclonable function  current-starved ring oscillator
	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517 作者:  Mu, Jianan;  Ren, Yi;  Wang, Wen;  Hu, Yizhong;  Chen, Shuai;  Chang, Chip-Hong;  Fan, Junfeng;  Ye, Jing;  Cao, Yuan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04 Memory access pattern  number theoretic transform (NTT)  post-quantum cryptography (PQC)  scalable hardware design
	An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 页码: 12 作者:  Cao, Yuan;  Wu, Yanze;  Wang, Wen;  Lu, Xu;  Chen, Shuai;  Ye, Jing;  Chang, Chip-Hong 收藏  |  浏览/下载：24/0  |  提交时间：2022/06/21 Hardware  Random access memory  Software algorithms  Quantum computing  Field programmable gate arrays  Computers  NIST  Post-quantum cryptography  eXtended Merkle signature scheme  hardware accelerator
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586 作者:  Chen, Shuai;  Li, Hao;  Chiang, Patrick Yin 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/13 All-digital clock and data recovery (ADCDR)  delay-locked loop (DLL)  forwarded-clock (FC) receiver  high-density interconnect  jitter tolerance  multicore processor  process variation  voltage and temperature drift