中国科学院计算技术研究所机构知识库

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限定条件	资助项目：National Natural Science Foundation of China[61376043]

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks 期刊论文 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2019, 卷号: 24, 期号: 1, 页码: 27 作者:  Li, Jiajun;  Yan, Guihai;  Lu, Wenyan;  Gong, Shijun;  Jiang, Shuhao;  Wu, Jingya;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/04/03 Deep neural networks  convolutional neural networks  accelerator  architecture  resource utilization  complementary effect
	Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 9, 页码: 2525-2537 作者:  Lu, Weina;  Hu, Yu;  Ye, Jing;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 Computer-aided design flow  field-programmable gate arrays (FPGAs)  hotspot optimization  performance
	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13 3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput
	Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 1, 页码: 92-102 作者:  Han, Yinhe;  Dong, Jianbo;  Weng, Kaiheng;  Wang, Ying;  Li, Xiaowei 收藏  |  浏览/下载：42/0  |  提交时间：2019/12/13 Endurance  phase-change random access memory (PRAM)  wear leveling (WL)