中国科学院计算技术研究所机构知识库

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限定条件	资助项目：National Natural Science Foundation of China[61221062]

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	A survey of neural network accelerators 期刊论文 FRONTIERS OF COMPUTER SCIENCE, 2017, 卷号: 11, 期号: 5, 页码: 746-761 作者:  Li, Zhen;  Wang, Yuqing;  Zhi, Tian;  Chen, Tianshi 收藏  |  浏览/下载：41/0  |  提交时间：2019/12/12 neural networks  accelerators  FPGAs  ASICs  DianNao series
	Articulation Points Guided Redundancy Elimination for Betweenness Centrality 期刊论文 ACM SIGPLAN NOTICES, 2016, 卷号: 51, 期号: 8, 页码: 73-86 作者:  Wang, Lei;  Yang, Fan;  Zhuang, Liangji;  Cui, Huimin;  Lv, Fang;  Feng, Xiaobing 收藏  |  浏览/下载：55/0  |  提交时间：2019/12/12 Algorithms  Performance  Partial Redundancy Elimination  Parallelism  Betweenness Centrality
	Predicting Cross-Core Performance Interference on Multicore Processors with Regression Analysis 期刊论文 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2016, 卷号: 27, 期号: 5, 页码: 1443-1456 作者:  Zhao, Jiacheng;  Cui, Huimin;  Xue, Jingling;  Feng, Xiaobing 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/13 Cross-core performance interference  memory subsystems  multicore processors  performance analysis  prediction model
	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13 3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput
	VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：35/0  |  提交时间：2019/12/13 Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)
	Multiple-combinational-channel: A network architecture for workload balance and deadlock free 期刊论文 FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE, 2016, 卷号: 56, 页码: 238-246 作者:  Chen, Liwei;  Wang, Yipeng;  Wang, Huandong;  Wang, Wenxiang;  Jing, Hua;  Zhang, Guangfei 收藏  |  浏览/下载：37/0  |  提交时间：2019/12/13 NoC  CC-NUMA  Channel  Load balance  Deadlock free
	Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 1, 页码: 92-102 作者:  Han, Yinhe;  Dong, Jianbo;  Weng, Kaiheng;  Wang, Ying;  Li, Xiaowei 收藏  |  浏览/下载：42/0  |  提交时间：2019/12/13 Endurance  phase-change random access memory (PRAM)  wear leveling (WL)