中国科学院计算技术研究所机构知识库

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限定条件	作者：Wang, Ying    第一作者

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Dadu-SV: Accelerate Stereo Vision Processing on NPU 期刊论文 IEEE EMBEDDED SYSTEMS LETTERS, 2022, 卷号: 14, 期号: 4, 页码: 191-194 作者:  Min, Feng;  Wang, Ying;  Xu, Haobo;  Huang, Junpei;  Wang, Yujie;  Zou, Xingqi;  Lu, Meixuan;  Han, Yinhe 收藏  |  浏览/下载：14/0  |  提交时间：2023/07/12 Hardware acceleration  neural computing  neural processing unit (NPU)  semiglobal matching (SGM)  stereo vision
	HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413 作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting 收藏  |  浏览/下载：25/0  |  提交时间：2022/12/07 Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)
	TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity 期刊论文 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 2022, 卷号: 16, 期号: 4, 页码: 636-650 作者:  Wang, Haibing;  He, Zhen;  Wang, Tengxiao;  He, Junxian;  Zhou, Xichuan;  Wang, Ying;  Liu, Liyuan;  Wu, Nanjian;  Tian, Min;  Shi, Cong 收藏  |  浏览/下载：13/0  |  提交时间：2023/07/12 Neurons  Neuromorphics  Hardware  System-on-chip  Field programmable gate arrays  Synapses  Self-organizing feature maps  Neuromorphic system  spiking neural network  spike-timing dependent plasticity  self-organizing map  reinforce- ment learning  on-chip learning
	CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2022, 卷号: 71, 期号: 7, 页码: 1626-1639 作者:  Zou, Kaiwei;  Wang, Ying;  Cheng, Long;  Qu, Songyun;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：29/0  |  提交时间：2022/12/07 Kernel  Computer architecture  Multicore processing  Deep learning  System-on-chip  Parallel processing  Real-time systems  Neural networks  parallel processing  real-time and embedded systems  single-chip multiprocessors  reinforcement learning  structured sparsity
	A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 卷号: 69, 期号: 3, 页码: 1657-1661 作者:  He, Zhen;  Shi, Cong;  Wang, Tengxiao;  Wang, Ying;  Tian, Min;  Zhou, Xichuan;  Li, Ping;  Liu, Liyuan;  Wu, Nanjian;  Luo, Gang 收藏  |  浏览/下载：24/0  |  提交时间：2022/12/07 Neurons  Hardware  System-on-chip  Costs  Training  Field programmable gate arrays  Computational modeling  Neuromorphic computing  spiking neural network  extreme learning machine  spike-timing-dependent plasticity  reward-modulated  on-chip learning
	A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification 期刊论文 SENSORS, 2020, 卷号: 20, 期号: 17, 页码: 18 作者:  He, Wei;  Huang, Jinguo;  Wang, Tengxiao;  Lin, Yingcheng;  He, Junxian;  Zhou, Xichuan;  Li, Ping;  Wang, Ying;  Wu, Nanjian;  Shi, Cong 收藏  |  浏览/下载：55/0  |  提交时间：2020/12/10 address-event representation (AER)  Random Ferns  object classification  neuromorphic hardware  online learning  on-chip learning
	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984 作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：68/0  |  提交时间：2019/12/10 Convolutional neural network (CNN)  deep learning  low power  memory subsystem
	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748 作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/12 Deep learning  error tolerance  neural network (NN)  timing variation
	STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296 作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/12 Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)