A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning

doi:10.1109/TCSII.2021.3117699

	A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning
	He, Zhen 1; Shi, Cong 1; Wang, Tengxiao 1; Wang, Ying 2; Tian, Min 1; Zhou, Xichuan 1; Li, Ping 1; Liu, Liyuan 3; Wu, Nanjian 3; Luo, Gang 4
	2022-03-01
发表期刊	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
ISSN	1549-7747
卷号	69 期号:3 页码:1657-1661
摘要	For embedded, mobile and edge-computing intelligent applications, this brief proposes a low-cost real-time neuromorphic hardware system of spiking Extreme Learning Machine (ELM) equipped with on-chip triplet-based reward-modulated spike-timing-dependent plasticity (R-STDP) learning capability. Our design employs a time-step pipelined dual-core architecture consisting of parallel computing unit arrays to improve processing speed, as well as a trace-assisting learning mechanism and on-the-fly hidden layer weight re-generators to significantly reduce hardware resource costs. Our architecture is scalable to different spiking ELM sizes under different tradeoffs among processing speed, recognition accuracy and resource costs. Tests showed that the on-chip triplet R-STDP learning capability can help to achieve relatively high recognition accuracies on our hardware system. An FPGA prototype with low logic and memory resource consumption was implemented, achieving 93% and 78.5% recognition accuracies on the MNIST and Fashion-MNIST image datasets, respectively, at a speed of 30 frames per second (fps) for inference and 22.5 fps for on-chip learning.
关键词	Neurons Hardware System-on-chip Costs Training Field programmable gate arrays Computational modeling Neuromorphic computing spiking neural network extreme learning machine spike-timing-dependent plasticity reward-modulated on-chip learning
DOI	10.1109/TCSII.2021.3117699
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[U20A20205] ; Key Project of Chongqing Science and Technology Foundation[cstc2019jcyj-zdxmX0017] ; State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences[CARCH201908]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000770045800202
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：11[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/18935
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Shi, Cong
作者单位	1.Chongqing Univ, Sch Microelect & Commun Engn, Chongqing 400044, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 3.Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China 4.Harvard Med Sch, Schepens Eye Res Inst, Dept Ophthalmol, Mass Eye & Ear, Boston, MA 02114 USA
推荐引用方式 GB/T 7714	He, Zhen,Shi, Cong,Wang, Tengxiao,et al. A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,2022,69(3):1657-1661.
APA	He, Zhen.,Shi, Cong.,Wang, Tengxiao.,Wang, Ying.,Tian, Min.,...&Luo, Gang.(2022).A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,69(3),1657-1661.
MLA	He, Zhen,et al."A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 69.3(2022):1657-1661.