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Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2115-2127
作者:  He, Yintao;  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：27/0  |  提交时间：2022/12/07
Computer architecture  Microprocessors  Resistance  Power demand  Training  Biological neural networks  Optimization  Low power (LP)  neural networks  processing-in-memory  resistive random-access memory (RRAM)  
Taming Process Variations in CNFET for Efficient Last-Level Cache Design 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 卷号: 30, 期号: 4, 页码: 418-431
作者:  Xu, Dawen;  Feng, Zhuangyu;  Liu, Cheng;  Li, Li;  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07
CNTFETs  Delays  Transistors  Layout  Very large scale integration  Radio frequency  Energy consumption  nanotube field-effect transistor (CNFET)  last-level cache (LLC)  process variation (PV)  variation-aware cache  
Architecting Effectual Computation for Machine Learning Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：88/0  |  提交时间：2020/12/10
Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits  
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984
作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：68/0  |  提交时间：2019/12/10
Convolutional neural network (CNN)  deep learning  low power  memory subsystem