中国科学院计算技术研究所机构知识库

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限定条件	作者：Han, Yinhe    第一作者    专题：英文    第一作者的第一单位    第一作者单位    通讯作者单位

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 9, 页码: 2889-2902 作者:  Liu, Rui;  Zhang, Xiaoyu;  Xie, Zhiwen;  Wang, Xinyu;  Li, Zerun;  Chen, Xiaoming;  Han, Yinhe;  Tang, Minghua 收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04 Computing-in-memory (CiM)  cryptographic algorithm  ferroelectric field-effect transistor (FeFET)  instruc-tion set architecture (ISA)
	Search-Free Inference Acceleration for Sparse Convolutional Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2156-2169 作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Wu, Jigang;  Chang, Liang;  Liu, Peng;  Xu, Haobo 收藏  |  浏览/下载：24/0  |  提交时间：2022/12/07 Internal interconnection  memory bandwidth  sparse accelerators  sparse convolution neural networks (CNNs)
	Integrating Two Logics Into One Crossbar Array for Logic Gate Design 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 卷号: 68, 期号: 8, 页码: 2987-2991 作者:  Yao, Lian;  Liu, Peng;  Wu, Jigang;  Han, Yinhe;  Zhong, Yuehang;  You, Zhiqiang 收藏  |  浏览/下载：38/0  |  提交时间：2021/12/01 Logic gates  Memristors  Logic arrays  Resistance  Logic functions  Adders  Switches  Logic gates  memristive crossbar  material implication  not material implication  1-bit full adder
	Swallow: A Versatile Accelerator for Sparse Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4881-4893 作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Xu, Haobo 收藏  |  浏览/下载：28/0  |  提交时间：2021/12/01 Accelerator  convolutional (Conv) layers  fully connected (FC) layers  sparse neural networks (SNNs)
	Architecting Effectual Computation for Machine Learning Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667 作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：89/0  |  提交时间：2020/12/10 Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits
	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277 作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：67/0  |  提交时间：2019/12/10 Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)
	On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 卷号: 17, 期号: 9, 页码: 1173-1186 作者:  Zhang, Lei;  Han, Yinhe;  Xu, Qiang;  Li, Xiao wei;  Li, Huawei 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/16 Defect tolerance  manycore system  network-on-chip  core-level redundancy  topology reconfiguration