Integrating Two Logics Into One Crossbar Array for Logic Gate Design

doi:10.1109/TCSII.2021.3071386

	Integrating Two Logics Into One Crossbar Array for Logic Gate Design
	Yao, Lian 1; Liu, Peng 1; Wu, Jigang 1; Han, Yinhe 2; Zhong, Yuehang 1; You, Zhiqiang 3,4
	2021-08-01
发表期刊	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
ISSN	1549-7747
卷号	68 期号:8 页码:2987-2991
摘要	Memristor-based crossbar array is one of the most promising structure for in-memory computing platforms. In a crossbar array, material implication logic (IMPLY) can be performed between different word lines or bit lines. Not-material implication (N-IMPLY) can only be performed between the bit lines. This brief demonstrates the feasibility of the execution of N-IMPLY logic between the word lines, followed by an approach for logic gate design in which two logics IMPLY and N-IMPLY are integrated into one crossbar array. Both two logics can be performed between the cells in different rows and columns within the crossbar. Six basic Boolean gates are implemented utilizing the proposed approach, with a lower number of operation steps and memristors compared to the IMPLY-only method. Moreover, a 1-bit full adder is implemented by utilizing the designed logic gates. The performance and area overhead have been improved by the proposed approach, in comparison to the existing methods.
关键词	Logic gates Memristors Logic arrays Resistance Logic functions Adders Switches Logic gates memristive crossbar material implication not material implication 1-bit full adder
DOI	10.1109/TCSII.2021.3071386
收录类别	SCI
语种	英语
资助项目	Guangdong Basic and Applied Basic Research Foundation[2021A1515011962] ; Guangdong Basic and Applied Basic Research Foundation[2019A1515110284] ; State Key Laboratory of Computer Architecture (ICT, CAC)[CARCH201907] ; National Natural Science Foundation of China[61672171] ; Guangdong Natural Science Foundation[2018B030311007] ; Major R&D Project of Educational Commission of Guangdong[2016KZDXM052] ; Guangdong Key R&D Project of China[2018B010107003]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000679532300051
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：3[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/17316
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Liu, Peng; Wu, Jigang
作者单位	1.Guangdong Univ Technol, Sch Comp Sci & Technol, Ctr High Performance Comp & Data Sci, Guangzhou 510006, Guangdong, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100190, Peoples R China 3.Hunan Univ, Coll Comp Sci & Elect Engn, Key Lab Embedded, Changsha 410082, Peoples R China 4.Hunan Univ, Network Comp Hunan Prov, Changsha 410082, Peoples R China
推荐引用方式 GB/T 7714	Yao, Lian,Liu, Peng,Wu, Jigang,et al. Integrating Two Logics Into One Crossbar Array for Logic Gate Design[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,2021,68(8):2987-2991.
APA	Yao, Lian,Liu, Peng,Wu, Jigang,Han, Yinhe,Zhong, Yuehang,&You, Zhiqiang.(2021).Integrating Two Logics Into One Crossbar Array for Logic Gate Design.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,68(8),2987-2991.
MLA	Yao, Lian,et al."Integrating Two Logics Into One Crossbar Array for Logic Gate Design".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 68.8(2021):2987-2991.