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Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 3, 页码: 878-891
作者:  Li, Hongyan;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20
Deep learning accelerator  deep neural network (DNN)  fp8 format  
Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762
作者:  Yang, Yinghao;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：6/0  |  提交时间：2024/05/20
FPGA accelerator  fully homomorphic encryption (FHE)  near data processing (NDP)  privacy computing  
SpecWands: An Efficient Priority-Based Scheduler Against Speculation Contention Attacks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4477-4490
作者:  Tang, Bowen;  Wu, Chenggang;  Yew, Pen-Chung;  Zhang, Yinqian;  Xie, Mengyao;  Lai, Yuanming;  Kang, Yan;  Wang, Wei;  Wei, Qiang;  Wang, Zhe
收藏  |  浏览/下载：8/0  |  提交时间：2024/05/20
Resource contention  scheduling strategy  simultaneous multithreading (SMT)  transient execution attack (TEA)  
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517
作者:  Mu, Jianan;  Ren, Yi;  Wang, Wen;  Hu, Yizhong;  Chen, Shuai;  Chang, Chip-Hong;  Fan, Junfeng;  Ye, Jing;  Cao, Yuan;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04
Memory access pattern  number theoretic transform (NTT)  post-quantum cryptography (PQC)  scalable hardware design  
Optimizing Training Efficiency and Cost of Hierarchical Federated Learning in Heterogeneous Mobile-Edge Cloud Computing 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1518-1531
作者:  Cui, Yangguang;  Cao, Kun;  Zhou, Junlong;  Wei, Tongquan
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
Training  Servers  Cloud computing  Delays  Costs  Computational modeling  Prototypes  Device frequency determination  federated learning (FL)  high efficiency  low cost  mobile-edge cloud computing (MECC)  user selection  
Swallow: A Versatile Accelerator for Sparse Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4881-4893
作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Xu, Haobo
收藏  |  浏览/下载：28/0  |  提交时间：2021/12/01
Accelerator  convolutional (Conv) layers  fully connected (FC) layers  sparse neural networks (SNNs)  
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4791-4804
作者:  Lan, Yazhu;  Nixon, Kent W.;  Guo, Qingli;  Zhang, Guohe;  Xu, Yuanchao;  Li, Hai;  Chen, Yiran
收藏  |  浏览/下载：41/0  |  提交时间：2021/12/01
Perturbation methods  Computational modeling  Data integrity  Detectors  Optimization  Field programmable gate arrays  Hardware  Adversarial attacks  confidence detection  deep neural networks (DNNs)  FPGA-based hardware architecture  sensor pattern noise (SPN)  
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4524-4536
作者:  Cui, Aijiao;  Li, Mengyang;  Qu, Gang;  Li, Huawei
收藏  |  浏览/下载：29/0  |  提交时间：2021/12/01
Ciphers  Encryption  Integrated circuits  Side-channel attacks  Testing  Cryptographic hash function  obfuscation logic  scan design  scan-based side-channel attack  
Architecting Effectual Computation for Machine Learning Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：88/0  |  提交时间：2020/12/10
Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits  
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 4, 页码: 803-815
作者:  Wu, Bi;  Dai, Pengcheng;  Cheng, Yuanqing;  Wang, Ying;  Yang, Jianlei;  Wang, Zhaohao;  Liu, Dijun;  Zhao, Weisheng
收藏  |  浏览/下载：52/0  |  提交时间：2020/12/10
System-on-chip  Computer architecture  Magnetic tunneling  Transistors  Switches  Thermal sensors  Organizations  Cache  data migration  low power  spin transfer torque magnetic memory (STT-MRAM)  thermal gradient