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PDG: A Prefetcher for Dynamic Graph Updating 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 4, 页码: 1246-1259
作者:  Zhang, Xinmiao;  Liu, Cheng;  Ni, Jiacheng;  Cheng, Yuanqing;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：3/0  |  提交时间：2024/05/20
Prefetching  Arrays  Optimization  Runtime  Heuristic algorithms  Computers  Monitoring  Computer architecture  data prefetching  memory system  
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 3, 页码: 878-891
作者:  Li, Hongyan;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20
Deep learning accelerator  deep neural network (DNN)  fp8 format  
Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762
作者:  Yang, Yinghao;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：6/0  |  提交时间：2024/05/20
FPGA accelerator  fully homomorphic encryption (FHE)  near data processing (NDP)  privacy computing  
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517
作者:  Mu, Jianan;  Ren, Yi;  Wang, Wen;  Hu, Yizhong;  Chen, Shuai;  Chang, Chip-Hong;  Fan, Junfeng;  Ye, Jing;  Cao, Yuan;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04
Memory access pattern  number theoretic transform (NTT)  post-quantum cryptography (PQC)  scalable hardware design  
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413
作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting
收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07
Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)  
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 9, 页码: 2808-2820
作者:  Wang, Yongchen;  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：31/0  |  提交时间：2022/12/07
Streaming media  Neural networks  Image coding  Decoding  Metadata  Deep learning  Hardware  Neural network acceleration  specialized accelerator  video analysis  
Architecting Effectual Computation for Machine Learning Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：89/0  |  提交时间：2020/12/10
Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits  
A QoS-QoR Aware CNN Accelerator Design Approach 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 11, 页码: 1995-2007
作者:  Wang, Ying;  Li, Huawei;  Cheng, Long;  Li, Xiaowei
收藏  |  浏览/下载：48/0  |  提交时间：2020/12/10
Approximate computing  convolutional neural network (CNN)  deep learning (DL)  quality of service (QoS)  real-time  
ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 8, 页码: 1438-1451
作者:  Lu, Hang;  Chang, Yisong;  Yan, Guihai;  Lin, Ning;  Wei, Xin;  Li, Xiaowei
收藏  |  浏览/下载：75/0  |  提交时间：2019/12/10
Many-core processors  networks-on-chip (NoCs)  power management  shuttle networks-on-chip (ShuttleNoC)  
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984
作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：68/0  |  提交时间：2019/12/10
Convolutional neural network (CNN)  deep learning  low power  memory subsystem