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Soft Error Reliability Analysis of Vision Transformers 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 页码: 11
作者:  Xue, Xinghua;  Liu, Cheng;  Wang, Ying;  Yang, Bing;  Luo, Tao;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
ABFT  fault-tolerance  soft errors  vision transformers (ViTs)  vulnerability analysis  
On-Line Fault Protection for ReRAM-Based Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2023, 卷号: 72, 期号: 2, 页码: 423-437
作者:  Li, Wen;  Wang, Ying;  Liu, Cheng;  He, Yintao;  Liu, Lian;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：14/0  |  提交时间：2023/07/12
Training  Fault detection  Computational modeling  Image edge detection  Memristors  Neural networks  Kernel  Deep neural network  hard fault  ReRAM  reliability  soft fault  
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413
作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting
收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07
Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)  
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 卷号: 29, 期号: 3, 页码: 472-484
作者:  Xu, Dawen;  Zhu, Ziyang;  Liu, Cheng;  Wang, Ying;  Zhao, Shuang;  Zhang, Lei;  Liang, Huaguo;  Li, Huawei;  Cheng, Kwang-Ting
收藏  |  浏览/下载：38/0  |  提交时间：2021/12/01
Neural networks  Circuit faults  Hardware  Acceleration  Reliability  Analytical models  Computational modeling  Integrated circuit reliability  reliability  
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 3, 页码: 714-727
作者:  Zhang, Ying;  Chakrabarty, Krishnendu;  Peng, Zebo;  Rezine, Ahmed;  Li, Huawei;  Eles, Petru;  Jiang, Jianhui
收藏  |  浏览/下载：51/0  |  提交时间：2020/12/10
Circuit faults  Built-in self-test  Out of order  Model checking  Integrated circuit modeling  Bounded model checking (BMC)  online testing  out-of-order superscalar processors  software-based self-testing (SBST)  
GPGPU-Based ATPG System: Myth or Reality? 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 1, 页码: 239-247
作者:  Lai, Liyang;  Tsai, Hans;  Li, Huawei
收藏  |  浏览/下载：49/0  |  提交时间：2020/12/10
ATPG  fault simulation  general-purpose computing on graphics processing units (GPGPUs)  
CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2016, 卷号: 65, 期号: 3, 页码: 716-729
作者:  Yan, Guihai;  Sun, Faqiang;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：39/0  |  提交时间：2019/12/13
Reliability  heterogeneity  healthy condition  manycore processor  
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：35/0  |  提交时间：2019/12/13
Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)  
LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs 期刊论文
INTEGRATION-THE VLSI JOURNAL, 2016, 卷号: 52, 页码: 41-50
作者:  Zhou, Jun;  Li, Huawei;  Wang, Tiancheng;  Li, Xiaowei
收藏  |  浏览/下载：46/0  |  提交时间：2019/12/13
Networks-on-chip  3D Mesh  Permanent fault  Fault-tolerance  Routing scheme  
Path Delay Test Generation Toward Activation of Worst Case Coupling Effects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 11, 页码: 1969-1982
作者:  Zhang, Minjin;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：73/0  |  提交时间：2019/12/16
Crosstalk-induced delay  delay testing  path delay fault  signal integrity  test generation  timing analysis