A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation

doi:10.1109/TVLSI.2017.2728609

	A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation
	Yuan, Luechao 1; Liu, Cang 1; Tang, Chuan 1; Huang, Shan 2; Chattopadhyay, Anupam 3; Ascheid, Gerd 4; Xing, Zuocheng 1
	2017-10-01
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
卷号	25 期号:10 页码:2789-2802
摘要	The fast-evolving standards of the wireless communication systems drive the demand for flexible baseband processing platforms. However, with the proliferation of MIMO technologies, traditional single-core-based solutions are hardly able to fulfill requirements with acceptable power and area cost. The reliance on multi-/many-core system is increasing. Different from the computation-limited single-core-based solutions, multi/many-core systems are often communication-limited. In this paper, aiming at MIMO interference cancellation algorithms, we propose a flexible master-slave-based multiprocessor system-on-chiparchitecture based on a systematically divide-and-conquer approach to optimize the communication problems from the application-, architecture-and programming-levels. First, a comprehensively analysis of several typical applications in terms of parallelism, communication patterns and computation patterns is presented. According to the analysis results, a low-complexity and flexible ad hoc point-to-point interconnected fine-grained programmable-element (f-PE) is proposed to execute the arithmetic calculation. In order to reduce the communicationtraffic, an f-PE-based slave-node is constructed to exploit the data and instruction localities of applications, and a master node that is used to schedule and serve data for the slave nodes is also integrated. Furthermore, to improve the ease of use of the architecture, a multiple instruction multiple datalikeprogramming model is adopted and an optimizing mapping strategy is developed. In order to show its flexibility potential, seven linear and nonlinear IC algorithms with distinct computation natures are implemented on the proposed architecture. Finally, the gate-level synthesis and postlayout results are presented to demonstrate the strength and weaknesses of our design.
关键词	Interference cancellation (IC) matrix inversion multiprocessor system-on-chip(MPSoC) parallel processing Tomlinson-Harashimaprecoding(THP)
DOI	10.1109/TVLSI.2017.2728609
收录类别	SCI
语种	英语
资助项目	NSF of China[61170083] ; Specialized Research Fund for the Doctoral Program of Higher Education[20114307110001] ; China Scholarship Council[CSC 201403170419]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000413751500010
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/6533
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Yuan, Luechao
作者单位	1.Natl Univ Def Technol, Natl Lab Parallel & Distributed Proc, Changsha 410073, Hunan, Peoples R China 2.Chinese Acad Sci, Wireless Commun Technol & Res Ctr, Inst Comp Technol, Bejing Key Lab Mobile Comp & Pervas Device, Beijing 100190, Peoples R China 3.Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore 4.Rhein Westfal TH Aachen, Inst Commun Technol & Embedded Syst, D-52056 Aachen, Germany
推荐引用方式 GB/T 7714	Yuan, Luechao,Liu, Cang,Tang, Chuan,et al. A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2017,25(10):2789-2802.
APA	Yuan, Luechao.,Liu, Cang.,Tang, Chuan.,Huang, Shan.,Chattopadhyay, Anupam.,...&Xing, Zuocheng.(2017).A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,25(10),2789-2802.
MLA	Yuan, Luechao,et al."A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25.10(2017):2789-2802.