Institute of Computing Technology, Chinese Academy IR
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning | |
Liu, Cheng1; Chu, Cheng1,2; Xu, Dawen1,2; Wang, Ying1; Wang, Qianlong1,2; Li, Huawei1; Li, Xiaowei1; Cheng, Kwang-Ting3 | |
2022-10-01 | |
发表期刊 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
ISSN | 0278-0070 |
卷号 | 41期号:10页码:3400-3413 |
摘要 | Hardware faults on the regular 2-D computing array of a typical deep learning accelerator (DLA) can lead to dramatic prediction accuracy loss. Prior redundancy design approaches typically have each homogeneous redundant processing element (PE) to mitigate faulty PEs for a limited region of the 2-D computing array rather than the entire computing array to avoid the excessive hardware overhead. However, they fail to recover the computing array when the number of faulty PEs in any region exceeds the number of redundant PEs in the same region. The mismatch problem deteriorates when the fault injection rate rises and the faults are unevenly distributed. To address the problem, we propose a hybrid computing architecture (HyCA) for fault-tolerant DLAs. It has a set of dot-production processing units (DPPUs) to recompute all the operations that are mapped to the faulty PEs despite the faulty PE locations. According to our experiments, HyCA shows significantly higher reliability, scalability, and performance with less chip area penalty when compared to the conventional redundancy approaches. Moreover, by taking advantage of the flexible recomputing, HyCA can also be utilized to scan the entire 2-D computing array and detect the faulty PEs effectively at runtime. |
关键词 | Circuit faults Computational modeling Deep learning Hardware Redundancy Neural networks Computer architecture Deep learning accelerator (DLA) fault detection fault tolerance hybrid computing architecture (HyCA) |
DOI | 10.1109/TCAD.2021.3124763 |
收录类别 | SCI |
语种 | 英语 |
资助项目 | National Key Research and Development Program of China[2020YFB1600201] ; National Natural Science Foundation of China[62174162] ; National Natural Science Foundation of China[61902375] ; National Natural Science Foundation of China[61834006] |
WOS研究方向 | Computer Science ; Engineering |
WOS类目 | Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic |
WOS记录号 | WOS:000856129900022 |
出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
引用统计 | |
文献类型 | 期刊论文 |
条目标识符 | http://119.78.100.204/handle/2XEOYT63/19415 |
专题 | 中国科学院计算技术研究所期刊论文_英文 |
通讯作者 | Xu, Dawen |
作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, SKLCA, Beijing 100080, Peoples R China 2.Hefei Univ Technol, Sch Microelect, Hefei 230009, Peoples R China 3.Hong Kong Univ Sci & Technol, Dept Comp Sci & Engn, Hong Kong, Peoples R China |
推荐引用方式 GB/T 7714 | Liu, Cheng,Chu, Cheng,Xu, Dawen,et al. HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2022,41(10):3400-3413. |
APA | Liu, Cheng.,Chu, Cheng.,Xu, Dawen.,Wang, Ying.,Wang, Qianlong.,...&Cheng, Kwang-Ting.(2022).HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,41(10),3400-3413. |
MLA | Liu, Cheng,et al."HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 41.10(2022):3400-3413. |
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