Path Delay Test Generation Toward Activation of Worst Case Coupling Effects

doi:10.1109/TVLSI.2010.2075945

	Path Delay Test Generation Toward Activation of Worst Case Coupling Effects
	Zhang, Minjin 1,2; Li, Huawei 1,2; Li, Xiaowei 1,2
	2011-11-01
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
卷号	19 期号:11 页码:1969-1982
摘要	As the feature size scales down, crosstalk noise on circuit timing becomes increasingly significant. In this paper, we propose a path delay test generation method toward activation of worst case crosstalk effects, in order to decrease the test escape of delay testing. The proposed method performs transition-map-based timing analysis to identify crosstalk-sensitive critical paths, followed by a deterministic test generation process. Using the transition map instead of the timing window to manage the timing information, the proposed method can identify many false coupling sites and thus reduce the pessimism in crosstalk-induced fault collection caused by inaccurate timing analysis. It can also efficiently calculate the accumulative crosstalk-induced delay, and find the sub-paths which cause worst case crosstalk effects during test generation. By converting the timing constraints of coupling lines into logic constraints, complex timing processing for crosstalk effect activation is avoided during test generation. In addition, the tradeoff between accuracy and efficiency can be explored by varying the size of timescale used in the transition map.
关键词	Crosstalk-induced delay delay testing path delay fault signal integrity test generation timing analysis
DOI	10.1109/TVLSI.2010.2075945
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China (NSFC)[60776031] ; National Natural Science Foundation of China (NSFC)[60633060] ; National Natural Science Foundation of China (NSFC)[60921002] ; National Basic Research Program of China (973)[2005CB321605] ; National Basic Research Program of China (973)[2011CB302501]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000294869500004
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：7[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/13090
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Zhang, Minjin
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100190, Peoples R China 2.Inst Automat, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Zhang, Minjin,Li, Huawei,Li, Xiaowei. Path Delay Test Generation Toward Activation of Worst Case Coupling Effects[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2011,19(11):1969-1982.
APA	Zhang, Minjin,Li, Huawei,&Li, Xiaowei.(2011).Path Delay Test Generation Toward Activation of Worst Case Coupling Effects.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,19(11),1969-1982.
MLA	Zhang, Minjin,et al."Path Delay Test Generation Toward Activation of Worst Case Coupling Effects".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 19.11(2011):1969-1982.