X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

doi:10.1109/TVLSI.2009.2019980

	X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing
	Li, Jia 1,2; Xu, Qiang 3,4,5; Hu, Yu ; Li, Xiaowei 1
	2010-07-01
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
卷号	18 期号:7 页码:1081-1092
摘要	Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capture phases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely "iFill", to address the above issue, by analyzing the impact of X-bits on switching activities of the circuit nodes in the two different phases. In addition, different from prior X-filling methods for shift-power reduction that can only reduce shift-in power, our method is able to cut down power consumptions in both shift-in and shift-out processes. Experimental results on benchmark circuits show that the proposed technique can guarantee the power safety in both shift and capture phases during at-speed scan-based testing.
关键词	At-speed scan-based testing low-power testing X-filling
DOI	10.1109/TVLSI.2009.2019980
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[60633060] ; National Natural Science Foundation of China[60803031] ; National Natural Science Foundation of China[90607010] ; National High Technology Research and Development Program of China (863 program)[2007AA01Z107] ; National High Technology Research and Development Program of China (863 program)[2007AA01Z113] ; National High Technology Research and Development Program of China (863 program)[2007AA01Z109] ; National Basic Research Program of China (973 program)[2005CB321604] ; National Basic Research Program of China (973 program)[2005CB321605] ; Hong Kong SAR Research Grants Council (RGC)[CUHK417406] ; Hong Kong SAR Research Grants Council (RGC)[CUHK417807] ; Hong Kong SAR Research Grants Council (RGC)[CUHK418708] ; NSFC[60876029] ; NSFC/RGC[N_CUHK417/08]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000278996600006
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：17[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/12043
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Li, Jia
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100190, Peoples R China 2.Chinese Acad Sci, Grad Univ, Beijing 100190, Peoples R China 3.Chinese Univ Hong Kong, Dept Comp Sci & Engn, CUHK Reliable Comp Lab CURE, Shatin, Hong Kong, Peoples R China 4.Chinese Univ Hong Kong, Dept Comp Sci & Engn, CUHK Reliable Comp Lab, CURE Lab, Hong Kong, Hong Kong, Peoples R China 5.CAS CUHK Shenzhen Inst Adv Integrat Technol, Shenzhen 518055, Peoples R China
推荐引用方式 GB/T 7714	Li, Jia,Xu, Qiang,Hu, Yu,et al. X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2010,18(7):1081-1092.
APA	Li, Jia,Xu, Qiang,Hu, Yu,&Li, Xiaowei.(2010).X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,18(7),1081-1092.
MLA	Li, Jia,et al."X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.7(2010):1081-1092.