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Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 1, 页码: 92-102
作者:  Han, Yinhe;  Dong, Jianbo;  Weng, Kaiheng;  Wang, Ying;  Li, Xiaowei
收藏  |  浏览/下载:42/0  |  提交时间:2019/12/13
Endurance  phase-change random access memory (PRAM)  wear leveling (WL)  
A signal degradation reduction method for memristor ratioed logic (MRL) gates 期刊论文
IEICE ELECTRONICS EXPRESS, 2015, 卷号: 12, 期号: 8, 页码: 6
作者:  Liu, Bosheng l;  Wang, Ying;  You, Zhiqiang;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载:39/0  |  提交时间:2019/12/13
full adder  memristor ratioed logic (MRL) gate  
ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2011, 卷号: 60, 期号: 9, 页码: 1219-1232
作者:  Yan, Guihai;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载:64/0  |  提交时间:2019/12/16
Lifetime reliability  self-adaptive  aging sensor  timing adaptation  NBTI  
Statistical lifetime reliability optimization considering joint effect of process variation and aging 期刊论文
INTEGRATION-THE VLSI JOURNAL, 2011, 卷号: 44, 期号: 3, 页码: 185-191
作者:  Jin, Song;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:67/0  |  提交时间:2019/12/16
Lifetime reliability  Process variation  NBTI  Duty cycle  Gate sizing  
BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission 期刊论文
IEICE TRANSACTIONS ON ELECTRONICS, 2008, 卷号: E91C, 期号: 10, 页码: 1690-1697
作者:  Yan, Guihai;  Han, Yinhe;  Li, Xiaowei;  Liu, Hui
收藏  |  浏览/下载:35/0  |  提交时间:2019/12/16
crosstalk delay  on-chip buses  bus-grouping transmission  asynchronous  shielding