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STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296
作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载:70/0  |  提交时间:2019/12/12
Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)  
Statistical lifetime reliability optimization considering joint effect of process variation and aging 期刊论文
INTEGRATION-THE VLSI JOURNAL, 2011, 卷号: 44, 期号: 3, 页码: 185-191
作者:  Jin, Song;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:67/0  |  提交时间:2019/12/16
Lifetime reliability  Process variation  NBTI  Duty cycle  Gate sizing  
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip 期刊论文
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, 卷号: E94D, 期号: 4, 页码: 809-821
作者:  Fu, Binzhang;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:70/0  |  提交时间:2019/12/16
network-on-chip (NoC)  fault-tolerant routing  multiple round dimension-order routing  turn model  
Compression/scan co-design for reducing test data volume, scan-in power dissipation, and test application time 期刊论文
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2006, 卷号: E89D, 期号: 10, 页码: 2616-2625
作者:  Hu, Yu;  Han, Yinhe;  Li, Xiaowei;  Li, Huawei;  Wen, Xiaoqing
收藏  |  浏览/下载:45/0  |  提交时间:2019/12/16
compression  run-length coding  random access scan  power dissipation  test application time