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VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:35/0  |  提交时间:2019/12/13
Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)  
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip 期刊论文
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, 卷号: E94D, 期号: 4, 页码: 809-821
作者:  Fu, Binzhang;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:70/0  |  提交时间:2019/12/16
network-on-chip (NoC)  fault-tolerant routing  multiple round dimension-order routing  turn model  
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 卷号: 17, 期号: 9, 页码: 1173-1186
作者:  Zhang, Lei;  Han, Yinhe;  Xu, Qiang;  Li, Xiao wei;  Li, Huawei
收藏  |  浏览/下载:38/0  |  提交时间:2019/12/16
Defect tolerance  manycore system  network-on-chip  core-level redundancy  topology reconfiguration  
Compression/scan co-design for reducing test data volume, scan-in power dissipation, and test application time 期刊论文
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2006, 卷号: E89D, 期号: 10, 页码: 2616-2625
作者:  Hu, Yu;  Han, Yinhe;  Li, Xiaowei;  Li, Huawei;  Wen, Xiaoqing
收藏  |  浏览/下载:45/0  |  提交时间:2019/12/16
compression  run-length coding  random access scan  power dissipation  test application time