中国科学院计算技术研究所机构知识库

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	DRONE: An Efficient Distributed Subgraph-Centric Framework for Processing Large-Scale Power-law Graphs 期刊论文 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2023, 卷号: 34, 期号: 2, 页码: 463-474 作者:  Zhang, Shuai;  Jiang, Zite;  Hou, Xingzhong;  Li, Mingyu;  Yuan, Mengting;  You, Haihang 收藏  |  浏览/下载：23/0  |  提交时间：2023/07/12 Fault tolerance  graph partition  large-scale power-law graph  parallel graph computation  subgraph-centric model
	Fault Modeling and Efficient Testing of Memristor-Based Memory 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 卷号: 68, 期号: 11, 页码: 4444-4455 作者:  Liu, Peng;  You, Zhiqiang;  Wu, Jigang;  Liu, Bosheng;  Han, Yinhe;  Chakrabarty, Krishnendu 收藏  |  浏览/下载：33/0  |  提交时间：2022/06/21 Electrical defects  fault model  defect-oriented testing  March algorithm  non-volatile memory
	A New Multiple-Round Dimension-Order Routing for Networks-on-Chip 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, 卷号: E94D, 期号: 4, 页码: 809-821 作者:  Fu, Binzhang;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：75/0  |  提交时间：2019/12/16 network-on-chip (NoC)  fault-tolerant routing  multiple round dimension-order routing  turn model
	VFSim: Concurrent fault simulation at register transfer level 期刊论文 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2005, 卷号: 20, 期号: 2, 页码: 175-186 作者:  Shen, L 收藏  |  浏览/下载：44/0  |  提交时间：2019/12/16 high-level testing  Verilog  RTL  circuit modeling  fault model  concurrent fault simulation