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RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, 页码: 11
作者:  Xu, Lida;  Cao, Zewen;  Zhao, Hualong;  Peng, Zhuo;  Miao, Yuchi;  Zhuang, Chunan;  Ruan, Hongrui;  Dong, Yuying;  Zeng, Chuanbin;  Li, Bo;  Luo, Jiajun
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Program processors  Hardware  Chip scale packaging  Design methodology  Costs  Object oriented modeling  Complexity theory  Testing  Registers  Prototypes  Agile methodology  object-oriented hardware  RISC-V  low-cost  integration  verification  open source