RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification

doi:10.1109/TCSI.2024.3509634

	RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification
	Xu, Lida 1,2,3; Cao, Zewen 1,2,3; Zhao, Hualong 4; Peng, Zhuo 4; Miao, Yuchi 5; Zhuang, Chunan 6; Ruan, Hongrui 1,2,3; Dong, Yuying 1,2,3; Zeng, Chuanbin 3,7; Li, Bo 3,7; Luo, Jiajun 7
	2024-12-10
发表期刊	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN	1549-8328
页码	11
摘要	Current processor chip designs are mainly oriented by performance, power and area (PPA), and developed using the waterfall model. However, there are two main challenges in this development model: 1) The end-to-end iteration cycle and cost of processor chip development are too high, and cannot flexibly respond to changes in chip fragmented design specifications. 2) Processor chip verification is less agile, and there is a lack of a full-chain processor agile design platform that can be easily ported to different development environments. To tackle both issues, we propose an object-oriented hardware agile design methodology, oriented by time, cost, and complexity, and have built the RIVL platform to support the agile development process for processors. RIVL integrates a highly automated design flow for processor RTL design, Integration, Verification, and Layout design to improve processor development efficiency. We achieved tape-out verification of more than 60 RISC-V processors through agile design methods, demonstrating the use and effectiveness of RIVL. We quantify the performance of CoreGen using CoreMark and demonstrate that CoreGen achieves industry-competitive performance.
关键词	Program processors Hardware Chip scale packaging Design methodology Costs Object oriented modeling Complexity theory Testing Registers Prototypes Agile methodology object-oriented hardware RISC-V low-cost integration verification open source
DOI	10.1109/TCSI.2024.3509634
收录类别	SCI
语种	英语
资助项目	Fund of Beijing Science and Technology Planning Project[Z231100005923015]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:001377402200001
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/41127
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Zhao, Hualong; Zeng, Chuanbin
作者单位	1.Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China 2.Univ Chinese Acad Sci, Sch Integrated Circuits, Beijing 100049, Peoples R China 3.Chinese Acad Sci, Key Lab Sci & Technol Silicon Devices, Beijing 100029, Peoples R China 4.Beijing Inst Open Source Chip, Beijing 100080, Peoples R China 5.Chinese Acad Sci, Inst Comp Technol, Beijing 100029, Peoples R China 6.Peng Cheng Lab, Shenzhen 518055, Guangdong, Peoples R China 7.Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
推荐引用方式 GB/T 7714	Xu, Lida,Cao, Zewen,Zhao, Hualong,et al. RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2024:11.
APA	Xu, Lida.,Cao, Zewen.,Zhao, Hualong.,Peng, Zhuo.,Miao, Yuchi.,...&Luo, Jiajun.(2024).RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,11.
MLA	Xu, Lida,et al."RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2024):11.