中国科学院计算技术研究所机构知识库

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	Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs 期刊论文 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2023, 卷号: 34, 期号: 12, 页码: 3133-3146 作者:  Liu, Bosheng;  Jiang, Zhuoshen;  Wu, Yalan;  Wu, Jigang;  Chen, Xiaoming;  Liu, Peng;  Zhou, Qingguo;  Han, Yinhe 收藏  |  浏览/下载：19/0  |  提交时间：2023/12/04 Frequency-domain accelerator  energy efficiency  resistive random access memory  frequency-domain convolutions
	Search-Free Inference Acceleration for Sparse Convolutional Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2156-2169 作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Wu, Jigang;  Chang, Liang;  Liu, Peng;  Xu, Haobo 收藏  |  浏览/下载：32/0  |  提交时间：2022/12/07 Internal interconnection  memory bandwidth  sparse accelerators  sparse convolution neural networks (CNNs)
	Fault Modeling and Efficient Testing of Memristor-Based Memory 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 卷号: 68, 期号: 11, 页码: 4444-4455 作者:  Liu, Peng;  You, Zhiqiang;  Wu, Jigang;  Liu, Bosheng;  Han, Yinhe;  Chakrabarty, Krishnendu 收藏  |  浏览/下载：33/0  |  提交时间：2022/06/21 Electrical defects  fault model  defect-oriented testing  March algorithm  non-volatile memory
	Swallow: A Versatile Accelerator for Sparse Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4881-4893 作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Xu, Haobo 收藏  |  浏览/下载：35/0  |  提交时间：2021/12/01 Accelerator  convolutional (Conv) layers  fully connected (FC) layers  sparse neural networks (SNNs)
	Accelerating DNN-based 3D point cloud processing for mobile computing 期刊论文 SCIENCE CHINA-INFORMATION SCIENCES, 2019, 卷号: 62, 期号: 11, 页码: 11 作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Li, Jiajun;  Xu, Haobo;  Li, Xiaowei 收藏  |  浏览/下载：234/0  |  提交时间：2019/12/10 deep neural network acceleration  point cloud data  neighbor point search  mobile robotics  hardware architecture
	A signal degradation reduction method for memristor ratioed logic (MRL) gates 期刊论文 IEICE ELECTRONICS EXPRESS, 2015, 卷号: 12, 期号: 8, 页码: 6 作者:  Liu, Bosheng l;  Wang, Ying;  You, Zhiqiang;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：45/0  |  提交时间：2019/12/13 full adder  memristor ratioed logic (MRL) gate