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DFU-E: A Dataflow Architecture for Edge DSP and AI Applications 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2025, 卷号: 36, 期号: 6, 页码: 1100-1114
作者:  Li, Wenming;  Fan, Zhihua;  Liu, Tianyu;  Wang, Zhen;  Wu, Haibin;  Wu, Meng;  Zhang, Kunming;  Liu, Yanhuan;  Sun, Ninghui;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：6/0  |  提交时间：2025/06/25
Artificial intelligence  Hardware  Edge computing  Computer architecture  Computational modeling  Single instruction multiple data  Energy efficiency  Target recognition  Radar polarimetry  Real-time systems  Dataflow architecture  edge computing  digital signal processing  AI  multi-layer dataflow mechanism  
Characterizing and Understanding HGNN Training on GPUs 期刊论文
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2025, 卷号: 22, 期号: 1, 页码: 25
作者:  Han, Dengke;  Yan, Mingyu;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：3/0  |  提交时间：2025/06/25
Heterogeneous graph neural networks  graph neural networks training  characterization  quantitative analysis  optimization guidelines  
Accelerating tensor multiplication by exploring hybrid product with hardware and software co-design 期刊论文
JOURNAL OF SYSTEMS ARCHITECTURE, 2025, 卷号: 159, 页码: 16
作者:  Zhang, Zhiyuan;  Fan, Zhihua;  Li, Wenming;  Qiu, Yuhang;  Wang, Zhen;  Ye, Xiaochun;  Fan, Dongrui;  An, Xuejun
收藏  |  浏览/下载：2/0  |  提交时间：2025/06/25
Tensor multiplication  Hybrid product  Dataflow  Accelerator  
SPMGAE: Self-purified masked graph autoencoders release robust expression power 期刊论文
NEUROCOMPUTING, 2025, 卷号: 611, 页码: 14
作者:  Song, Shuhan;  Li, Ping;  Dun, Ming;  Zhang, Yuan;  Cao, Huawei;  Ye, Xiaochun
收藏  |  浏览/下载：27/0  |  提交时间：2024/12/06
Graph neural networks  Masked graph autoencoders  Robustness  Graph adversarial attacks  
HiHGNN: Accelerating HGNNs Through Parallelism and Data Reusability Exploitation 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2024, 卷号: 35, 期号: 7, 页码: 1122-1138
作者:  Xue, Runzhen;  Han, Dengke;  Yan, Mingyu;  Zou, Mo;  Yang, Xiaocheng;  Wang, Duo;  Li, Wenming;  Tang, Zhimin;  Kim, John;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：22/0  |  提交时间：2024/12/06
Semantics  Parallel processing  Graph neural networks  Vectors  Graphics processing units  Fuses  Hardware  GNN  GNN accelerator  graph neural network  HGNN  HGNN accelerator  heterogeneous graph neural network  
MoDSE: A High-Accurate Multiobjective Design Space Exploration Framework for CPU Microarchitectures 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 5, 页码: 1525-1537
作者:  Wang, Duo;  Yan, Mingyu;  Teng, Yihan;  Han, Dengke;  Liu, Xin;  Li, Wenming;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：28/0  |  提交时间：2024/12/06
Pareto optimization  Predictive models  Measurement  Space exploration  Prediction algorithms  Central Processing Unit  Microarchitecture  CPU microarchitecture  design space exploration (DSE)  multiobjective exploration  Pareto hypervolume  prediction model  
Improving Utilization of Dataflow Unit for Multi-Batch Processing 期刊论文
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2024, 卷号: 21, 期号: 1, 页码: 26
作者:  Fan, Zhihua;  Li, Wenming;  Wang, Zhen;  Yang, Yu;  Ye, Xiaochun;  Fan, Dongrui;  Sun, Ninghui;  An, Xuejun
收藏  |  浏览/下载：33/0  |  提交时间：2024/05/20
Utilization  network-on-chip  decoupled architecture  batch processing  
DPQ: dynamic pseudo-mean mixed-precision quantization for pruned neural network 期刊论文
MACHINE LEARNING, 2024, 页码: 14
作者:  Pei, Songwen;  Wang, Jiyao;  Zhang, Bingxue;  Qin, Wei;  Xue, Hai;  Ye, Xiaochun;  Chen, Mingsong
收藏  |  浏览/下载：33/0  |  提交时间：2024/05/20
Big data  Compression  Deep learning  Pseudo-mean mixed-precision quantization  Pruned neural network  
Accelerating Convolutional Neural Networks by Exploiting the Sparsity of Output Activation 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2023, 卷号: 34, 期号: 12, 页码: 3253-3265
作者:  Fan, Zhihua;  Li, Wenming;  Wang, Zhen;  Liu, Tianyu;  Wu, Haibin;  Liu, Yanhuan;  Wu, Meng;  Wu, Xinxin;  Ye, Xiaochun;  Fan, Dongrui;  Sun, Ninghui;  An, Xuejun
收藏  |  浏览/下载：30/0  |  提交时间：2024/05/20
Accelerator  output activation  prediction  sparse convolutional neural network  
Design of a Compact Superconducting RSFQ Register File 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 页码: 8
作者:  Zhang, Kuozhong;  Zhang, Zhimin;  Tang, Guangming;  Ye, Xiaochun
收藏  |  浏览/下载：36/0  |  提交时间：2023/12/04
Registers  Clocks  Josephson junctions  Power transmission lines  Logic gates  Decoding  Program processors  RSFQ  register file  superconducting digital circuit