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Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 2, 页码: 603-616
作者:  Du, Yibo;  Wang, Ying;  Wang, Mengdi;  Li, Xiaowei;  Han, Yinhe
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Hardware  Chiplets  Homomorphic encryption  Polynomials  Vectors  Scheduling algorithms  Noise  Program processors  Design automation  Computational efficiency  Chiplet  fully homomorphic encryption (FHE)  hardware-software co-design  heterogeneous architecture  
Systematic Methodology of Modeling and Design Space Exploration for CMOS Image Sensors 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 2, 页码: 1047-1060
作者:  Ma, Tianrui;  Gao, Zhe;  Chen, Zhe;  Kakarala, Ramakrishna;  Shan, Charles;  Cao, Weidong;  Zhang, Xuan
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
CMOS image sensors (CIS)  design space explo ration (DSE)  integrated circuit modeling  integrated circuit modeling  
LayerTEE: Decoupled Memory Protection for Scalable Multilayer Communication on RISC-V 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 1, 页码: 533-546
作者:  Pan, Shangjie;  Yang, Yinghao;  Peng, Xuanyao;  Zhao, Xiquan;  Du, Dong;  Lu, Hang;  Xia, Yubin;  Li, Xiaowei
收藏  |  浏览/下载：0/0  |  提交时间：2026/05/25
Cryptography  Security  Cloud computing  Scalability  Protection  Memory management  Hardware  Communication systems  Software  Program processors  Communication  memory isolation  RISC-V  trusted execution environment (TEE)  
A RISC-V Extended Infrastructure for CNNs Through Pipelined Computing and Data Dependence Optimization 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 11, 页码: 4141-4154
作者:  Luo, Teng;  Xia, Tengfei;  Chen, Jiayuan;  Fan, Zhihua;  Li, Wenming;  Mu, Yudong;  An, Xuejun;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：24/0  |  提交时间：2025/12/03
Artificial intelligence  Convolution  Convolutional neural networks  Computer architecture  Computational efficiency  Pipelines  Logic  Filters  Fans  Biological system modeling  Convolutional neural networks (CNNs) acceleration  dataflow optimization  pipelined computing  RISC-V extended instructions  
SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3962-3975
作者:  Jin, Pengwei;  Fan, Zhe;  Zhao, Yongwei;  Du, Zidong;  Guo, Hongrui;  Nan, Ziyuan;  Hao, Yifan;  Li, Chongxiao;  Ma, Tianyun;  Zhang, Zhenxing;  Li, Xiaqing;  Li, Wei;  Hu, Xing;  Guo, Qi;  Xu, Zhiwei;  Chen, Tianshi
收藏  |  浏览/下载：25/0  |  提交时间：2025/12/03
IP networks  Hardware  Graphics processing units  Central Processing Unit  Programming  Software  Pipelines  System-on-chip  Process control  Neural networks  Hardware heterogeneity  system architectures  System-on-Chip (SoC)  
OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3830-3843
作者:  Ni, Liwei;  Wang, Rui;  Liu, Miao;  Meng, Xingyu;  Lin, Xiaoze;  Liu, Junfeng;  Luo, Guojie;  Chu, Zhufei;  Qian, Weikang;  Yang, Xiaoyan;  Xie, Biwei;  Li, Xingquan;  Li, Huawei
收藏  |  浏览/下载：28/0  |  提交时间：2025/12/03
Logic  Logic gates  Delays  Optimization  Machine learning  Hardware design languages  Boolean functions  Computer science  Benchmark testing  Wire  Adaptive  application  dataset  logic synthesis  machine learning (ML)  
GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3816-3829
作者:  Fan, Haishuang;  Meng, Rui;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：19/0  |  提交时间：2025/12/03
Field programmable gate arrays  Redundancy  Indexes  Graphics processing units  Central Processing Unit  Integrated circuit modeling  Computational modeling  Engines  Design automation  Data models  Accelerator  FPGA  Graph processing  
Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3451-3464
作者:  Fan, Haishuang;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：29/0  |  提交时间：2025/12/03
Binary sequences  Streaming media  Decoding  Artificial neural networks  Superresolution  Kernel  Engines  Design automation  Video codecs  Throughput  Accelerator  codec  FPGA  super-resolution (SR)  
SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3490-3503
作者:  Xue, Runzhen;  Yan, Mingyu;  Han, Dengke;  Xiao, Ziheng;  Tang, Zhimin;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：22/0  |  提交时间：2025/12/03
Semantics  Layout  Graph neural networks  Optimization  Vectors  Graphics processing units  Feature extraction  Design automation  Training  Hardware acceleration  Graph neural network (GNN)  hardware accelerator  heterogeneous graph neural network (HGNN)  semantic graph  
Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3409-3422
作者:  Long, Boyu;  Han, Yinhe;  Sun, Xian-He;  Chen, Xiaoming
收藏  |  浏览/下载：20/0  |  提交时间：2025/12/03
Logic  Computer architecture  Integrated circuit interconnections  Hardware  Routing  Circuits  Table lookup  Decoding  Performance evaluation  Logic gates  Processing in memory  resistive random-access memory (RRAM)  software-hardware co-design  ternary content-addressable memory (TCAM)