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PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 5, 页码: 1745-1759
作者:  Sun, Xiaotian;  Wang, Xinyu;  Li, Wanqian;  Han, Yinhe;  Chen, Xiaoming
收藏  |  浏览/下载：5/0  |  提交时间：2025/06/25
Hardware  Optimization  Artificial neural networks  Pipelines  Parallel processing  Biological system modeling  Resource management  Adaptation models  Scheduling  Memory management  Deep neural network (DNN)  end-to-end compiler  processing-in-memory (PIM) accelerator  system-level optimization  
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 5, 页码: 1887-1900
作者:  Chen, Xiaoming
收藏  |  浏览/下载：3/0  |  提交时间：2025/06/25
SPICE  Sparse matrices  Parallel processing  Design automation  Vectors  Scalability  Linear systems  Upper bound  Performance evaluation  Numerical stability  Circuit simulation  parallel linear solver  sparse linear solver  
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 2, 页码: 737-750
作者:  Ma, Tianyun;  Wen, Yuanbo;  Song, Xinkai;  Jin, Pengwei;  Huang, Di;  Han, Husheng;  Nan, Ziyuan;  Yu, Zhongkai;  Peng, Shaohui;  Zhao, Yongwei;  Chen, Huaping;  Du, Zidong;  Hu, Xing;  Guo, Qi
收藏  |  浏览/下载：6/0  |  提交时间：2025/06/25
Skeleton  Optimization  Graphics processing units  Vectors  Hardware  Artificial neural networks  Accuracy  Deep symbolic regression (DSR)  radial basis function network (RBFN)  transcendental functions  unified array  
On Modeling and Detecting Trojans in Instruction Sets 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 10, 页码: 3226-3239
作者:  Zhang, Ying;  He, Aodi;  Li, Jiaying;  Rezine, Ahmed;  Peng, Zebo;  Larsson, Erik;  Yang, Tao;  Jiang, Jianhui;  Li, Huawei
收藏  |  浏览/下载：15/0  |  提交时间：2024/12/06
Trojan horses  Security  Program processors  Companies  Inspection  Hardware security  Reverse engineering  Deep test for security  hidden instruction Trojan (HIT)  unbounded model checking (UMC)  VLSI test  
A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 9, 页码: 2635-2646
作者:  He, Yintao;  Li, Bing;  Wang, Ying;  Liu, Cheng;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：23/0  |  提交时间：2024/12/06
Task analysis  Sparse matrices  Convolution  Convolutional neural networks  Design automation  Neural networks  Integrated circuits  Graph convolutional network  hardware acceleration  processing-in-memory  
An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 6, 页码: 1781-1793
作者:  Chen, Mingkai;  Liu, Cheng;  Liang, Shengwen;  He, Lei;  Wang, Ying;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：23/0  |  提交时间：2024/12/06
Memory management  Buildings  Bandwidth  Hardware  Social networking (online)  Energy efficiency  Parallel processing  Graph construction  graph updating  near-data processing  nearest neighbors  power gating  stacked memory  
General Purpose Deep Learning Accelerator Based on Bit Interleaving 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 5, 页码: 1470-1483
作者:  Chang, Liang;  Lu, Hang;  Li, Chenglong;  Zhao, Xin;  Hu, Zhicheng;  Zhou, Jun;  Li, Xiaowei
收藏  |  浏览/下载：27/0  |  提交时间：2024/12/06
Synchronization  Parallel processing  Computational modeling  Training  Pragmatics  Power demand  Hardware acceleration  Accelerator  bit-level sparsity  deep neural network (DNN)  
An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 5, 页码: 1497-1510
作者:  Liu, Lian;  Wang, Ying;  Zhao, Xiandong;  Chen, Weiwei;  Li, Huawei;  Li, Xiaowei;  Han, Yinhe
收藏  |  浏览/下载：52/0  |  提交时间：2024/12/06
Optimization  Quantization (signal)  Computer architecture  Training  Computational modeling  Integrated circuit modeling  Convergence  Automatic joint optimization  efficient model inference  network quantization  neural architecture search (NAS)  
MoDSE: A High-Accurate Multiobjective Design Space Exploration Framework for CPU Microarchitectures 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 5, 页码: 1525-1537
作者:  Wang, Duo;  Yan, Mingyu;  Teng, Yihan;  Han, Dengke;  Liu, Xin;  Li, Wenming;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：28/0  |  提交时间：2024/12/06
Pareto optimization  Predictive models  Measurement  Space exploration  Prediction algorithms  Central Processing Unit  Microarchitecture  CPU microarchitecture  design space exploration (DSE)  multiobjective exploration  Pareto hypervolume  prediction model  
PDG: A Prefetcher for Dynamic Graph Updating 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 4, 页码: 1246-1259
作者:  Zhang, Xinmiao;  Liu, Cheng;  Ni, Jiacheng;  Cheng, Yuanqing;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：29/0  |  提交时间：2024/05/20
Prefetching  Arrays  Optimization  Runtime  Heuristic algorithms  Computers  Monitoring  Computer architecture  data prefetching  memory system