中文版 | English

在结果中检索

CSpace

浏览/检索结果: 共79条，第1-10条 帮助

已选(0)清除 条数/页：   排序方式：
A RISC-V Extended Infrastructure for CNNs Through Pipelined Computing and Data Dependence Optimization 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 11, 页码: 4141-4154
作者:  Luo, Teng;  Xia, Tengfei;  Chen, Jiayuan;  Fan, Zhihua;  Li, Wenming;  Mu, Yudong;  An, Xuejun;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Artificial intelligence  Convolution  Convolutional neural networks  Computer architecture  Computational efficiency  Pipelines  Logic  Filters  Fans  Biological system modeling  Convolutional neural networks (CNNs) acceleration  dataflow optimization  pipelined computing  RISC-V extended instructions  
SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3962-3975
作者:  Jin, Pengwei;  Fan, Zhe;  Zhao, Yongwei;  Du, Zidong;  Guo, Hongrui;  Nan, Ziyuan;  Hao, Yifan;  Li, Chongxiao;  Ma, Tianyun;  Zhang, Zhenxing;  Li, Xiaqing;  Li, Wei;  Hu, Xing;  Guo, Qi;  Xu, Zhiwei;  Chen, Tianshi
收藏  |  浏览/下载：5/0  |  提交时间：2025/12/03
IP networks  Hardware  Graphics processing units  Central Processing Unit  Programming  Software  Pipelines  System-on-chip  Process control  Neural networks  Hardware heterogeneity  system architectures  System-on-Chip (SoC)  
OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3830-3843
作者:  Ni, Liwei;  Wang, Rui;  Liu, Miao;  Meng, Xingyu;  Lin, Xiaoze;  Liu, Junfeng;  Luo, Guojie;  Chu, Zhufei;  Qian, Weikang;  Yang, Xiaoyan;  Xie, Biwei;  Li, Xingquan;  Li, Huawei
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Logic  Logic gates  Delays  Optimization  Machine learning  Hardware design languages  Boolean functions  Computer science  Benchmark testing  Wire  Adaptive  application  dataset  logic synthesis  machine learning (ML)  
GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3816-3829
作者:  Fan, Haishuang;  Meng, Rui;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Field programmable gate arrays  Redundancy  Indexes  Graphics processing units  Central Processing Unit  Integrated circuit modeling  Computational modeling  Engines  Design automation  Data models  Accelerator  FPGA  Graph processing  
Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3451-3464
作者:  Fan, Haishuang;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Binary sequences  Streaming media  Decoding  Artificial neural networks  Superresolution  Kernel  Engines  Design automation  Video codecs  Throughput  Accelerator  codec  FPGA  super-resolution (SR)  
SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3490-3503
作者:  Xue, Runzhen;  Yan, Mingyu;  Han, Dengke;  Xiao, Ziheng;  Tang, Zhimin;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Semantics  Layout  Graph neural networks  Optimization  Vectors  Graphics processing units  Feature extraction  Design automation  Training  Hardware acceleration  Graph neural network (GNN)  hardware accelerator  heterogeneous graph neural network (HGNN)  semantic graph  
Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3409-3422
作者:  Long, Boyu;  Han, Yinhe;  Sun, Xian-He;  Chen, Xiaoming
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Logic  Computer architecture  Integrated circuit interconnections  Hardware  Routing  Circuits  Table lookup  Decoding  Performance evaluation  Logic gates  Processing in memory  resistive random-access memory (RRAM)  software-hardware co-design  ternary content-addressable memory (TCAM)  
Shallow Quantum Circuit Implementation of Symmetric Functions With Limited Ancillary Qubits 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 8, 页码: 3060-3072
作者:  Zi, Wei;  Nie, Junhong;  Sun, Xiaoming
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Qubit  Quantum circuit  Logic gates  Hamming weight  Quantum state  Boolean functions  Machine learning  Sun  Optimization  Hamming distances  quantum circuit optimization  quantum circuit synthesis  quantum computing  symmetric function  upper bound  
Oxpecker: Leaking Secrets via Fetch Target Queue 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 7, 页码: 2461-2474
作者:  Li, Shan;  Xu, Zheliang;  Shen, Haihua;  Li, Huawei
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Program processors  Prefetching  Security  Pipelines  Integrated circuits  Design automation  Prevention and mitigation  Manuals  Decoding  Optimization  Branch prediction unit (BPU)  fetch target queue (FTQ)  front-end  hardware security  instruction fetch unit  instruction prefetcher  
Improving DNN Accuracy on MLC PIM via Non-Ideal PIM Device Fine-Tuning 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 6, 页码: 2277-2286
作者:  Lv, Hao;  Zhang, Lei;  Wang, Ying
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Closed box  Accuracy  Computational modeling  Programming  Training  Optimization  Computer architecture  Semiconductor device modeling  Energy efficiency  Artificial neural networks  Black-box  multilevel cell (MLC) resistive random access memory (RRAM)  model fine-tuning  processing-in-memory (PIM)