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无权访问的条目 学位论文
作者:  蒲宇宁
Adobe PDF(4620Kb)  |  收藏  |  浏览/下载：2/1  |  提交时间：2016/07/01
Towards connection-scalable RNIC architecture 期刊论文
JOURNAL OF SUPERCOMPUTING, 2024, 页码: 25
作者:  Kang, Ning;  Wang, Zhan;  Yang, Fan;  Ma, Xiaoxiao;  Ma, Zhenlong;  Yuan, Guojun;  Tan, Guangming
收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20
Architecture design  Network Interface Card (NIC)  Remote Direct Memory Access (RDMA)  Scalability problem  
Improving Utilization of Dataflow Unit for Multi-Batch Processing 期刊论文
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2024, 卷号: 21, 期号: 1, 页码: 26
作者:  Fan, Zhihua;  Li, Wenming;  Wang, Zhen;  Yang, Yu;  Ye, Xiaochun;  Fan, Dongrui;  Sun, Ninghui;  An, Xuejun
收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20
Utilization  network-on-chip  decoupled architecture  batch processing  
Chip design with machine learning: a survey from algorithm perspective 期刊论文
SCIENCE CHINA-INFORMATION SCIENCES, 2023, 卷号: 66, 期号: 11, 页码: 31
作者:  He, Wenkai;  Li, Xiaqing;  Song, Xinkai;  Hao, Yifan;  Zhang, Rui;  Du, Zidong;  Chen, Yunji
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
chip design  machine learning  chip design automation  design result estimation  design optimization and correction  design construction  
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 页码: 14
作者:  Cao, Yuan;  Liu, Wanyi;  Zheng, Yue;  Chen, Shuai;  Ye, Jing;  Qian, Lei;  Chang, Chip-Hong
收藏  |  浏览/下载：8/0  |  提交时间：2023/12/04
Entropy  Authentication  System-on-chip  Protocols  Jitter  Computer architecture  Rail to rail outputs  True random number generator  physical unclonable function  current-starved ring oscillator  
Design of a Compact Superconducting RSFQ Register File 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 页码: 8
作者:  Zhang, Kuozhong;  Zhang, Zhimin;  Tang, Guangming;  Ye, Xiaochun
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
Registers  Clocks  Josephson junctions  Power transmission lines  Logic gates  Decoding  Program processors  RSFQ  register file  superconducting digital circuit  
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses 期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2023, 卷号: 28, 期号: 4, 页码: 23
作者:  Chu, Cheng;  Liu, Cheng;  Xu, Dawen;  Wang, Ying;  Luo, Tao;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
Deformable convolution network  neural network accelerator  irregular memory access  runtime tile scheduling  
Toward Developing High-Performance RISC-V Processors Using Agile Methodology 期刊论文
IEEE MICRO, 2023, 卷号: 43, 期号: 4, 页码: 98-106
作者:  Xu, Yinan;  Yu, Zihao;  Tang, Dan;  Cai, Ye;  Huan, Dandan;  He, Wei;  Sun, Ninghui;  Bao, Yungang
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
Program processors  Behavioral sciences  Chip scale packaging  Microarchitecture  Hardware  Analytical models  Layout  
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517
作者:  Mu, Jianan;  Ren, Yi;  Wang, Wen;  Hu, Yizhong;  Chen, Shuai;  Chang, Chip-Hong;  Fan, Junfeng;  Ye, Jing;  Cao, Yuan;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04
Memory access pattern  number theoretic transform (NTT)  post-quantum cryptography (PQC)  scalable hardware design  
TCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design 期刊论文
JOURNAL OF SYSTEMS ARCHITECTURE, 2023, 卷号: 136, 页码: 12
作者:  Li, Wenqing;  Liu, Tianyi;  Xiao, Ziyuan;  Qi, Han;  Zhu, Weipu;  Wang, Jian
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
Heterogeneous system  Tightly coupled  Accelerator design framework  Interaction latency  Low-latency task