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A survey of neural network accelerators 期刊论文
FRONTIERS OF COMPUTER SCIENCE, 2017, 卷号: 11, 期号: 5, 页码: 746-761
作者:  Li, Zhen;  Wang, Yuqing;  Zhi, Tian;  Chen, Tianshi
收藏  |  浏览/下载：41/0  |  提交时间：2019/12/12
neural networks  accelerators  FPGAs  ASICs  DianNao series  
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：35/0  |  提交时间：2019/12/13
Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)  
Multiple-combinational-channel: A network architecture for workload balance and deadlock free 期刊论文
FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE, 2016, 卷号: 56, 页码: 238-246
作者:  Chen, Liwei;  Wang, Yipeng;  Wang, Huandong;  Wang, Wenxiang;  Jing, Hua;  Zhang, Guangfei
收藏  |  浏览/下载：37/0  |  提交时间：2019/12/13
NoC  CC-NUMA  Channel  Load balance  Deadlock free  
An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2016, 卷号: 65, 期号: 2, 页码: 367-381
作者:  Ma, Jun;  Yan, Guihai;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载：36/0  |  提交时间：2019/12/13
Heterogeneous manycores  scale-out  scale-up  analytical model  power efficiency  runtime management  
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586
作者:  Chen, Shuai;  Li, Hao;  Chiang, Patrick Yin
收藏  |  浏览/下载：38/0  |  提交时间：2019/12/13
All-digital clock and data recovery (ADCDR)  delay-locked loop (DLL)  forwarded-clock (FC) receiver  high-density interconnect  jitter tolerance  multicore processor  process variation  voltage and temperature drift