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Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 11, 页码: 5071-5084
作者:  Zhang, Xiaoyu;  Liu, Rui;  Song, Tao;  Yang, Yuxin;  Han, Yinhe;  Chen, Xiaoming
收藏  |  浏览/下载:13/0  |  提交时间:2023/07/12
Convolutional neural network (CNN)  ferroelectric field-effect transistor (FeFET)  few-shot learning  in-memory processing  ternary content-addressable memory (TCAM)  
Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing 期刊论文
IEEE EMBEDDED SYSTEMS LETTERS, 2022, 卷号: 14, 期号: 3, 页码: 155-158
作者:  Xiao, Hang;  Xu, Haobo;  Chen, Xiaoming;  Wang, Yujie;  Han, Yinhe
收藏  |  浏览/下载:29/0  |  提交时间:2022/12/07
Approximate computing  convolution neural network  multiply and accumulate (MAC)  
LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks 期刊论文
IEEE COMPUTER ARCHITECTURE LETTERS, 2022, 卷号: 21, 期号: 1, 页码: 29-32
作者:  Xiao, Hang;  Xu, Haobo;  Wang, Ying;  Wang, Yujie;  Han, Yinhe
收藏  |  浏览/下载:21/0  |  提交时间:2022/12/07
Linear particle accelerator  Correlation  Kernel  Convolution  Linear regression  System-on-chip  Quantization (signal)  Neural network  acceleration  convolution  linear regression  bit-sparsity  
Swallow: A Versatile Accelerator for Sparse Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4881-4893
作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Xu, Haobo
收藏  |  浏览/下载:28/0  |  提交时间:2021/12/01
Accelerator  convolutional (Conv) layers  fully connected (FC) layers  sparse neural networks (SNNs)  
Architecting Effectual Computation for Machine Learning Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:88/0  |  提交时间:2020/12/10
Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits  
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296
作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载:70/0  |  提交时间:2019/12/12
Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)