CSpace

浏览/检索结果: 共6条,第1-6条 帮助

限定条件        
已选(0)清除 条数/页:   排序方式:
LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks 期刊论文
IEEE COMPUTER ARCHITECTURE LETTERS, 2022, 卷号: 21, 期号: 1, 页码: 29-32
作者:  Xiao, Hang;  Xu, Haobo;  Wang, Ying;  Wang, Yujie;  Han, Yinhe
收藏  |  浏览/下载:21/0  |  提交时间:2022/12/07
Linear particle accelerator  Correlation  Kernel  Convolution  Linear regression  System-on-chip  Quantization (signal)  Neural network  acceleration  convolution  linear regression  bit-sparsity  
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277
作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载:67/0  |  提交时间:2019/12/10
Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)  
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296
作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载:70/0  |  提交时间:2019/12/12
Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)  
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 卷号: 23, 期号: 12, 页码: 3053-3064
作者:  Lu, Hang;  Fu, Binzhang;  Wang, Ying;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei
收藏  |  浏览/下载:39/0  |  提交时间:2019/12/13
Cloud processor  networks-on-chip (NoCs)  performance isolation  relaxed isolation (RISO)  workload consolidation  
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip 期刊论文
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, 卷号: E94D, 期号: 4, 页码: 809-821
作者:  Fu, Binzhang;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:70/0  |  提交时间:2019/12/16
network-on-chip (NoC)  fault-tolerant routing  multiple round dimension-order routing  turn model  
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 卷号: 17, 期号: 9, 页码: 1173-1186
作者:  Zhang, Lei;  Han, Yinhe;  Xu, Qiang;  Li, Xiao wei;  Li, Huawei
收藏  |  浏览/下载:38/0  |  提交时间:2019/12/16
Defect tolerance  manycore system  network-on-chip  core-level redundancy  topology reconfiguration