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A modified post-TnL vertex cache for the multi-shader embedded GPUs 期刊论文
IEICE ELECTRONICS EXPRESS, 2015, 卷号: 12, 期号: 10, 页码: 12
作者:  Wei, Jizeng;  Chang, Yisong;  Li, Bingchao;  Guo, Wei;  Sun, Jizhou
收藏  |  浏览/下载:45/0  |  提交时间:2019/12/13
computer graphics  embedded GPU  vertex cache  vertex/unified shader  triangle strip  
A signal degradation reduction method for memristor ratioed logic (MRL) gates 期刊论文
IEICE ELECTRONICS EXPRESS, 2015, 卷号: 12, 期号: 8, 页码: 6
作者:  Liu, Bosheng l;  Wang, Ying;  You, Zhiqiang;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载:39/0  |  提交时间:2019/12/13
full adder  memristor ratioed logic (MRL) gate