A modified post-TnL vertex cache for the multi-shader embedded GPUs

doi:10.1587/elex.12.20150314

	A modified post-TnL vertex cache for the multi-shader embedded GPUs
	Wei, Jizeng 1; Chang, Yisong 2; Li, Bingchao 1; Guo, Wei 1; Sun, Jizhou 1
	2015-05-25
发表期刊	IEICE ELECTRONICS EXPRESS
ISSN	1349-2543
卷号	12 期号:10 页码:12
摘要	The traditional post-TnL vertex cache (abbr. 'dpost-VC') in embedded GPUs (EGPUs) with only one vertex or unified shader does not fit to multi-shader EGPUs for two reasons. As multiple shaders run in parallelism, (a) the out-of-order vertex processing may raise the post-VC inconsistency that leads to cache the error data, and (b) it is very hard to detect in time which vertices are saved in the post-VC in the stage of vertex fetching, resulting in the low performance. In this paper, we propose a modified post-VC including a decoupling cache and a vertex batch in-order commit controller, which can guarantee that the data SRAM and index tag can be updated in-order according to the same replacement policy in the different stages of vertex processing. The function of the proposed post-VC is verified on a FPGA-based platform. Experimental results show that it increases the performance by an average of 172% and 80.6% compared to the EGPU without/with the traditional post-VC respectively at a little expense.
关键词	computer graphics embedded GPU vertex cache vertex/unified shader triangle strip
DOI	10.1587/elex.12.20150314
收录类别	SCI
语种	英语
资助项目	Natural Science Foundation of China[61402321] ; Natural Science Foundation of Tianjin
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000358125900009
出版者	IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/9566
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wei, Jizeng
作者单位	1.Tianjin Univ, Sch Comp Sci & Technol, Beijing, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, Beijing 100864, Peoples R China
推荐引用方式 GB/T 7714	Wei, Jizeng,Chang, Yisong,Li, Bingchao,et al. A modified post-TnL vertex cache for the multi-shader embedded GPUs[J]. IEICE ELECTRONICS EXPRESS,2015,12(10):12.
APA	Wei, Jizeng,Chang, Yisong,Li, Bingchao,Guo, Wei,&Sun, Jizhou.(2015).A modified post-TnL vertex cache for the multi-shader embedded GPUs.IEICE ELECTRONICS EXPRESS,12(10),12.
MLA	Wei, Jizeng,et al."A modified post-TnL vertex cache for the multi-shader embedded GPUs".IEICE ELECTRONICS EXPRESS 12.10(2015):12.