中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2789-2802 作者:  Yuan, Luechao;  Liu, Cang;  Tang, Chuan;  Huang, Shan;  Chattopadhyay, Anupam;  Ascheid, Gerd;  Xing, Zuocheng 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/12 Interference cancellation (IC)  matrix inversion  multiprocessor system-on-chip(MPSoC)  parallel processing  Tomlinson-Harashimaprecoding(THP)
	A New Binary-Halved Clustering Method and ERT Processor for ASSR System 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1871-1884 作者:  Chou, Chih-Hung;  Kuan, Ta-Wen;  Barma, Shovan;  Chen, Bo-Wei;  Ji, Wen;  Peng, Chih-Hsiang;  Wang, Jhing-Fa 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/13 Automatic speech-speaker recognition (ASSR)  binary-halved clustering (BHC)  configurable processing element (CPE)  extraction  recognition  and training (ERT)  multichannel router (MCR)  multifeedback shift register (MFSR)
	VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：35/0  |  提交时间：2019/12/13 Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586 作者:  Chen, Shuai;  Li, Hao;  Chiang, Patrick Yin 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/13 All-digital clock and data recovery (ADCDR)  delay-locked loop (DLL)  forwarded-clock (FC) receiver  high-density interconnect  jitter tolerance  multicore processor  process variation  voltage and temperature drift
	X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 卷号: 18, 期号: 7, 页码: 1081-1092 作者:  Li, Jia;  Xu, Qiang;  Hu, Yu;  Li, Xiaowei 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/16 At-speed scan-based testing  low-power testing  X-filling