中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 卷号: 27, 期号: 8, 页码: 1851-1860 作者:  Wu, Bi;  Zhang, Beibei;  Cheng, Yuanqing;  Wang, Ying;  Liu, Dijun;  Zhao, Weisheng 收藏  |  浏览/下载：77/0  |  提交时间：2019/12/10 Error correction code (ECC)  last level cache (LLC)  reliability  spin-transfer-torque magnetoresistive random-access memory (STT-MRAM)  temperature
	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748 作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/12 Deep learning  error tolerance  neural network (NN)  timing variation
	Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 9, 页码: 2525-2537 作者:  Lu, Weina;  Hu, Yu;  Ye, Jing;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 Computer-aided design flow  field-programmable gate arrays (FPGAs)  hotspot optimization  performance
	STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296 作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/12 Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)
	Data Remapping for Static NUCA in Degradable Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 卷号: 23, 期号: 5, 页码: 879-892 作者:  Wang, Ying;  Zhang, Lei;  Han, Yin-He;  Li, Hua-Wei;  Li, Xiaowei 收藏  |  浏览/下载：37/0  |  提交时间：2019/12/13 Chip multiprocessor (CMP)  fault tolerant  network-on-chip (NoC)  nonuniform cache architecture (NUCA)
	Path Delay Test Generation Toward Activation of Worst Case Coupling Effects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 11, 页码: 1969-1982 作者:  Zhang, Minjin;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：73/0  |  提交时间：2019/12/16 Crosstalk-induced delay  delay testing  path delay fault  signal integrity  test generation  timing analysis