中国科学院计算技术研究所机构知识库

浏览/检索结果: 共4条，第1-4条

帮助

限定条件	出处：IEEE TRANSACTIONS ON COMPUTERS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Multi-Node Acceleration for Large-Scale GCNs 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2022, 卷号: 71, 期号: 12, 页码: 3140-3152 作者:  Sun, Gongjian;  Yan, Mingyu;  Wang, Duo;  Li, Han;  Li, Wenming;  Ye, Xiaochun;  Fan, Dongrui;  Xie, Yuan 收藏  |  浏览/下载：26/0  |  提交时间：2023/07/12 Deep learning  graph neural network  hardware accelerator  multi-node system  communication optimization
	EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2021, 卷号: 70, 期号: 9, 页码: 1511-1525 作者:  Liang, Shengwen;  Wang, Ying;  Liu, Cheng;  He, Lei;  Li, Huawei;  Xu, Dawen;  Li, Xiaowei 收藏  |  浏览/下载：38/0  |  提交时间：2021/12/01 Neural networks  Hardware  System-on-chip  Task analysis  Feature extraction  Memory management  Graph neural network  accelerator architecture  hardware acceleration
	SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2019, 卷号: 68, 期号: 11, 页码: 1663-1677 作者:  Li, Jiajun;  Jiang, Shuhao;  Gong, Shijun;  Wu, Jingya;  Yan, Junchao;  Yan, Guihai;  Li, Xiaowei 收藏  |  浏览/下载：41/0  |  提交时间：2020/12/10 Convolutional neural networks  accelerator architecture  hardware acceleration
	Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2019, 卷号: 68, 期号: 6, 页码: 867-881 作者:  Lu, Wenyan;  Yan, Guihai;  Li, Jiajun;  Gong, Shijun;  Jiang, Shuhao;  Wu, Jingya;  Li, Xiaowei 收藏  |  浏览/下载：249/0  |  提交时间：2019/08/16 Convolutional neural networks  accelerator  architecture  parallelism  sparsity