中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 11, 页码: 4313-4324 作者:  Xu, Jiaen;  Wang, Xiaohang;  Jiang, Yingtao;  Singh, Amit Kumar;  Gu, Chongyan;  Huang, Letian;  Yang, Mei;  Li, Shunbin 收藏  |  浏览/下载：13/0  |  提交时间：2023/07/12 Block coding  inter-packet delay  network-on-chip (NoC)  secure channel
	Structured Decomposition for Reversible Boolean Functions 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2410-2421 作者:  Jiang, Jiaqing;  Sun, Xiaoming;  Sun, Yuan;  Wu, Kewen;  Xia, Zhiyu 收藏  |  浏览/下载：41/0  |  提交时间：2020/12/10 Integrated circuits  logic gates  quantum computation  reversible computation  reversible logic  synthesis method
	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277 作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：67/0  |  提交时间：2019/12/10 Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)