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Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2115-2127
作者:  He, Yintao;  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:27/0  |  提交时间:2022/12/07
Computer architecture  Microprocessors  Resistance  Power demand  Training  Biological neural networks  Optimization  Low power (LP)  neural networks  processing-in-memory  resistive random-access memory (RRAM)  
A Fast Precision Tuning Solution for Always-On DNN Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 5, 页码: 1236-1248
作者:  Wang, Ying;  He, Yintao;  Cheng, Long;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:25/0  |  提交时间:2022/12/07
Computer architecture  Neural networks  Computational modeling  Approximate computing  Tuning  Switches  Microprocessors  Always-on  CNN  computing-in-memory (CiM)  resistive RAM  
Toward Efficient Execution of Mainstream Deep Learning Frameworks on Mobile Devices: Architectural Implications 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, 卷号: 40, 期号: 3, 页码: 453-466
作者:  Dai, Yuting;  Zhang, Rui;  Xue, Rui;  Liu, Benyong;  Li, Tao
收藏  |  浏览/下载:41/0  |  提交时间:2021/12/01
Deep learning  Mobile handsets  Performance evaluation  Mobile applications  Computational modeling  Quantization (signal)  Central Processing Unit  CPU usage  deep learning (DL)  energy efficiency  microarchitecture  mobile phone  network compression  thermal characterization  
Architecting Effectual Computation for Machine Learning Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:88/0  |  提交时间:2020/12/10
Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits  
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984
作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载:68/0  |  提交时间:2019/12/10
Convolutional neural network (CNN)  deep learning  low power  memory subsystem  
Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 卷号: 34, 期号: 8, 页码: 1223-1235
作者:  Du, Zidong;  Lingamneni, Avinash;  Chen, Yunji;  Palem, Krishna V.;  Temam, Olivier;  Wu, Chengyong
收藏  |  浏览/下载:54/0  |  提交时间:2019/12/13
Accelerator architectures  energy efficient  hardware neuron network  inexact computing