中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762 作者:  Yang, Yinghao;  Lu, Hang;  Li, Xiaowei 收藏  |  浏览/下载：6/0  |  提交时间：2024/05/20 FPGA accelerator  fully homomorphic encryption (FHE)  near data processing (NDP)  privacy computing
	Search-Free Inference Acceleration for Sparse Convolutional Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2156-2169 作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Wu, Jigang;  Chang, Liang;  Liu, Peng;  Xu, Haobo 收藏  |  浏览/下载：24/0  |  提交时间：2022/12/07 Internal interconnection  memory bandwidth  sparse accelerators  sparse convolution neural networks (CNNs)
	Addressing Sparsity in Deep Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 10, 页码: 1858-1871 作者:  Zhou, Xuda;  Du, Zidong;  Zhang, Shijin;  Zhang, Lei;  Lan, Huiying;  Liu, Shaoli;  Li, Ling;  Guo, Qi;  Chen, Tianshi;  Chen, Yunji 收藏  |  浏览/下载：257/0  |  提交时间：2019/12/10 Accelerator  architecture  deep neural networks (DNNs)  sparsity
	ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 8, 页码: 1438-1451 作者:  Lu, Hang;  Chang, Yisong;  Yan, Guihai;  Lin, Ning;  Wei, Xin;  Li, Xiaowei 收藏  |  浏览/下载：75/0  |  提交时间：2019/12/10 Many-core processors  networks-on-chip (NoCs)  power management  shuttle networks-on-chip (ShuttleNoC)
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh