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中国科学院计算技术研究所机构知识库
Institute of Computing Technology, Chinese Academy IR
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中国科学院计算技术研... [6]
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收录类别:SCI
出处:IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
作者:Li, Xiaowei
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Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture
期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762
作者:
Yang, Yinghao
;
Lu, Hang
;
Li, Xiaowei
收藏
  |  
浏览/下载:6/0
  |  
提交时间:2024/05/20
FPGA accelerator
fully homomorphic encryption (FHE)
near data processing (NDP)
privacy computing
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation
期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517
作者:
Mu, Jianan
;
Ren, Yi
;
Wang, Wen
;
Hu, Yizhong
;
Chen, Shuai
;
Chang, Chip-Hong
;
Fan, Junfeng
;
Ye, Jing
;
Cao, Yuan
;
Li, Huawei
;
Li, Xiaowei
收藏
  |  
浏览/下载:9/0
  |  
提交时间:2023/12/04
Memory access pattern
number theoretic transform (NTT)
post-quantum cryptography (PQC)
scalable hardware design
Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing
期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2115-2127
作者:
He, Yintao
;
Wang, Ying
;
Li, Huawei
;
Li, Xiaowei
收藏
  |  
浏览/下载:28/0
  |  
提交时间:2022/12/07
Computer architecture
Microprocessors
Resistance
Power demand
Training
Biological neural networks
Optimization
Low power (LP)
neural networks
processing-in-memory
resistive random-access memory (RRAM)
A Fast Precision Tuning Solution for Always-On DNN Accelerators
期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 5, 页码: 1236-1248
作者:
Wang, Ying
;
He, Yintao
;
Cheng, Long
;
Li, Huawei
;
Li, Xiaowei
收藏
  |  
浏览/下载:26/0
  |  
提交时间:2022/12/07
Computer architecture
Neural networks
Computational modeling
Approximate computing
Tuning
Switches
Microprocessors
Always-on
CNN
computing-in-memory (CiM)
resistive RAM
Architecting Effectual Computation for Machine Learning Accelerators
期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:
Lu, Hang
;
Zhang, Mingzhe
;
Han, Yinhe
;
Wang, Qi
;
Li, Huawei
;
Li, Xiaowei
收藏
  |  
浏览/下载:89/0
  |  
提交时间:2020/12/10
Computational modeling
Throughput
Adders
Machine learning
Acceleration
Kernel
Computational efficiency
Accelerator architectures
neural network hardware
multiplying circuits
ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors
期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 8, 页码: 1438-1451
作者:
Lu, Hang
;
Chang, Yisong
;
Yan, Guihai
;
Lin, Ning
;
Wei, Xin
;
Li, Xiaowei
收藏
  |  
浏览/下载:75/0
  |  
提交时间:2019/12/10
Many-core processors
networks-on-chip (NoCs)
power management
shuttle networks-on-chip (ShuttleNoC)
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators
期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984
作者:
Wang, Ying
;
Li, Huawei
;
Li, Xiaowei
收藏
  |  
浏览/下载:68/0
  |  
提交时间:2019/12/10
Convolutional neural network (CNN)
deep learning
low power
memory subsystem