A signal degradation reduction method for memristor ratioed logic (MRL) gates

doi:10.1587/elex.12.20150062

	A signal degradation reduction method for memristor ratioed logic (MRL) gates
	Liu, Bosheng l 1,2; Wang, Ying 1,2; You, Zhiqiang 3; Han, Yinhe 1,2; Li, Xiaowei 1,2
	2015-04-25
发表期刊	IEICE ELECTRONICS EXPRESS
ISSN	1349-2543
卷号	12 期号:8 页码:6
摘要	This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a study case. Compared to the previous MRL-based standard cell design, the proposed circuit can reduce 11.1% memristor cells, 22.2% CMOS transistors, 38.9% vias, 58% power. Compared to the previous MRL-based optimized design, the proposed design can reduce 11.1% memristor cells, 12.5% CMOS transistors, 98.1% power, 98.1% energy.
关键词	full adder memristor ratioed logic (MRL) gate
DOI	10.1587/elex.12.20150062
收录类别	SCI
语种	英语
资助项目	National Basic Research Program of China (973)[2011CB302503] ; National Natural Science Foundation of China (NSFC)[6110001661221062]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000358123700002
出版者	IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
引用统计	被引频次：5[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/9570
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Liu, Bosheng l
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100864, Peoples R China 2.Univ Chinese Acad Sci, Beijing, Peoples R China 3.Hunan Univ, Coll Comp Sci & Elect Engn, Changsha 410082, Hunan, Peoples R China
推荐引用方式 GB/T 7714	Liu, Bosheng l,Wang, Ying,You, Zhiqiang,et al. A signal degradation reduction method for memristor ratioed logic (MRL) gates[J]. IEICE ELECTRONICS EXPRESS,2015,12(8):6.
APA	Liu, Bosheng l,Wang, Ying,You, Zhiqiang,Han, Yinhe,&Li, Xiaowei.(2015).A signal degradation reduction method for memristor ratioed logic (MRL) gates.IEICE ELECTRONICS EXPRESS,12(8),6.
MLA	Liu, Bosheng l,et al."A signal degradation reduction method for memristor ratioed logic (MRL) gates".IEICE ELECTRONICS EXPRESS 12.8(2015):6.