LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization

doi:10.1587/transinf.2016EDP7184

	LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization
	Hu, Yu 1,2; Ye, Jing 2; Shi, Zhiping 1,3; Li, Xiaowei 2
	2017-02-01
发表期刊	IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
ISSN	1745-1361
卷号	E100D 期号:2 页码:323-331
摘要	Process variation has become prominent in the advanced CMOS technology, making the timing of fabricated circuits more uncertain. In this paper, we propose a Layout-Aware Path Selection (LAPS) technique to accurately estimate the circuit timing variation from a small set of paths. Three features of paths are considered during the path selection. Experiments conducted on benchmark circuits with process variation simulated with VARIUS show that, by selecting only hundreds of paths, the fitting errors of timing distribution are kept below 5.3% when both spatial correlated and spatial uncorrelated process variations exist.
关键词	process variation timing variation sample path selection least square
DOI	10.1587/transinf.2016EDP7184
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China (NSFC)[61532017] ; National Natural Science Foundation of China (NSFC)[61376043] ; National Natural Science Foundation of China (NSFC)[61274030]
WOS研究方向	Computer Science
WOS类目	Computer Science, Information Systems ; Computer Science, Software Engineering
WOS记录号	WOS:000399370700009
出版者	IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
引用统计	被引频次：4[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/7286
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Shi, Zhiping
作者单位	1.Capital Normal Univ, Beijing Adv Innovat Ctr Imaging Technol, Beijing 100048, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 3.Capital Normal Univ, Coll Informat Engn, Beijing 100048, Peoples R China
推荐引用方式 GB/T 7714	Hu, Yu,Ye, Jing,Shi, Zhiping,et al. LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,2017,E100D(2):323-331.
APA	Hu, Yu,Ye, Jing,Shi, Zhiping,&Li, Xiaowei.(2017).LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization.IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,E100D(2),323-331.
MLA	Hu, Yu,et al."LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization".IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E100D.2(2017):323-331.