A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators

doi:10.1109/TCAD.2017.2778060

	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators
	Wang, Ying; Li, Huawei; Li, Xiaowei
	2018-10-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	37 期号:10 页码:1971-1984
摘要	The rapid development of machine learning is enabling a plenty of novel applications, such as image and speech recognition for embedded and mobile devices. However, state-of-the-art deep learning models like convolutional neural networks (CNNs) are demanding so much on-chip storage and compute resources that they cannot be smoothly handled by low-power mobile or embedded systems. In order to fit large CNN models into mobile or more cutting-edge devices for IoT or cyberphysics applications, we proposed an efficient on-chip memory architecture for CNN inference acceleration, and showed its application to in-house single-instruction multiple-data structure machine learning processor. The redesigned on-chip memory subsystem, Memsqueezer, includes an active weight buffer and data buffer set that embraces specialized compression methods to reduce the footprint of CNN parameters (weights) and activation data, respectively. Memsqueezer buffer can compress the data and weight set according to the dataflow in computation, and it also includes a built-in redundancy detection mechanism that actively scans through the working-set of CNNs to boost their inference performance by eliminating the computation redundancy in CNN models. In our experiments, it is shown that the CNN processors with Memsqueezer buffers achieve more than 2x performance improvement and reduces 85% energy consumption on average over the conventional buffer design with the same area budget.
关键词	Convolutional neural network (CNN) deep learning low power memory subsystem
DOI	10.1109/TCAD.2017.2778060
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[61432017] ; National Natural Science Foundation of China[61504153] ; National Natural Science Foundation of China[61532017] ; National Natural Science Foundation of China[61402146] ; National Natural Science Foundation of China[61521092] ; National Key Research and Development Program of China[2016YFF0203500]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:000445264200005
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：11[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/4917
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Li, Huawei; Li, Xiaowei
作者单位	Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Wang, Ying,Li, Huawei,Li, Xiaowei. A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2018,37(10):1971-1984.
APA	Wang, Ying,Li, Huawei,&Li, Xiaowei.(2018).A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,37(10),1971-1984.
MLA	Wang, Ying,et al."A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 37.10(2018):1971-1984.