Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM

doi:10.1109/TC.2019.2900036

	Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM
	Zhang, Mingzhe 1; Zhang, Lunkai 2; Jiang, Lei 3; Chong, Frederic T.2; Liu, Zhiyong 1
	2019-09-01
发表期刊	IEEE TRANSACTIONS ON COMPUTERS
ISSN	0018-9340
卷号	68 期号:9 页码:1365-1375
摘要	MLC PCM provides high-density data storage and extended data retention; therefore it is a promising alternative for DRAM main memory. However, its low write performance is a major obstacle to commercialization. One opportunity for improving the latency of MLC PCM writes is to use fewer SET iterations in a single write. Unfortunately, this comes with a cost: the data written by these short writes have remarkably shorter retentions and thus need frequent refreshes. As a result, it is impractical to use these short-latency, short-retention writes globally. In this paper, we analyze the temporal behavior of write operations in typical applications and show that the write operations are bursty in nature, that is, during some time intervals the memory is subject to a large number of writes, while during other time intervals there hardly any memory operations take place. Based on this observation, we propose Quick-and-Dirty (QnD), a lightweight scheme to improve the performance of MLC PCM. When the write performance becomes the system bottleneck, QnD performs some write operations using the short-latency, short-retention write mode. Then, when the memory system is relatively quiet, QnD uses idle-memory intervals to refresh the data written by short-latency, short-retention writes in order to mitigate the short retention problem. Our experimental results show that QnD improves performance by 30.9 percent on geometric mean while still providing acceptable memory lifetime (7.58 years on geometric mean). We also provide sensitivity studies of the aggressiveness, memory coverage and granularity of QnD technique.
关键词	MLC PCM performance lifetime retention time tradeoff
DOI	10.1109/TC.2019.2900036
收录类别	SCI
语种	英语
资助项目	NSFC[61761136014] ; NSFC[61520106005] ; NSFC[61521092]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000480341500009
出版者	IEEE COMPUTER SOC
引用统计	被引频次：4[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/4450
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Liu, Zhiyong
作者单位	1.Chinese Acad Sci, ICT, State Key Lab Comp Architecture, Beijing 100864, Peoples R China 2.Univ Chicago, Chicago, IL 60637 USA 3.Indiana Univ, Bloomington, IN 47405 USA
推荐引用方式 GB/T 7714	Zhang, Mingzhe,Zhang, Lunkai,Jiang, Lei,et al. Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM[J]. IEEE TRANSACTIONS ON COMPUTERS,2019,68(9):1365-1375.
APA	Zhang, Mingzhe,Zhang, Lunkai,Jiang, Lei,Chong, Frederic T.,&Liu, Zhiyong.(2019).Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM.IEEE TRANSACTIONS ON COMPUTERS,68(9),1365-1375.
MLA	Zhang, Mingzhe,et al."Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM".IEEE TRANSACTIONS ON COMPUTERS 68.9(2019):1365-1375.