An Efficient Paillier Homomorphic Encryption Circuit With Optional CRT Acceleration for IoT

doi:10.1109/JIOT.2025.3603982

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	An Efficient Paillier Homomorphic Encryption Circuit With Optional CRT Acceleration for IoT
	Feng, Jundong 1; Zhang, Xiaoliang 1; Zilic, Zeljko 2; Hao, Qinfen 3; Wang, Junchao 1
	2025-11-15
发表期刊	IEEE INTERNET OF THINGS JOURNAL
ISSN	2327-4662
卷号	12 期号:22 页码:48146-48158
摘要	The Paillier scheme, widely recognized as the most prevalent additive homomorphic encryption paradigm, faces significant challenges in Internet of Things (IoT) applications due to latency, power, and hardware overhead. This article proposes an efficient Paillier homomorphic encryption circuit for IoT, integrating Chinese remainder theorem (CRT) acceleration. First, we propose an algorithm framework tailored for hardware reuse that supports multiple functionalities of the Paillier scheme. It introduces an montgomery modular multiplication (MMM) algorithm with superior area-time product (ATP) to implement core computations, and reduces hardware cost by reusing MMM to replace other computational units. Then, a computational unit reuse architecture based on the algorithmic framework is designed to reduce resource overhead. Moreover, a split-coupled MMM circuit design is proposed to counteract computational resource expansion induced by CRT operations. The hardware design is synthesized under SMIC 40 nm CMOS technology. The evaluation shows that the proposed scheme provides a high-performance Paillier circuit design with less area and lower power, offering an effective solution for data security processing in IoT.
关键词	Hardware Internet of Things Homomorphic encryption Computational efficiency Computer architecture Software Parallel processing Optimization Costs Circuit synthesis Chinese remainder theorem (CRT) circuit homomorphic encryption Internet of Things (IoT) paillier
DOI	10.1109/JIOT.2025.3603982
收录类别	SCI
语种	英语
WOS研究方向	Computer Science ; Engineering ; Telecommunications
WOS类目	Computer Science, Information Systems ; Engineering, Electrical & Electronic ; Telecommunications
WOS记录号	WOS:001611106800029
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/43106
专题	中国科学院计算技术研究所
通讯作者	Wang, Junchao
作者单位	1.Chongqing Univ, Dept Microelect & Commun Engn, Chongqing 400044, Peoples R China 2.McGill Univ, Dept Elect & Comp Engn, Montreal, PQ H3A 0G4, Canada 3.Chinese Acad Sci, Inst Comp Technol, Beijing 100045, Peoples R China
推荐引用方式 GB/T 7714	Feng, Jundong,Zhang, Xiaoliang,Zilic, Zeljko,et al. An Efficient Paillier Homomorphic Encryption Circuit With Optional CRT Acceleration for IoT[J]. IEEE INTERNET OF THINGS JOURNAL,2025,12(22):48146-48158.
APA	Feng, Jundong,Zhang, Xiaoliang,Zilic, Zeljko,Hao, Qinfen,&Wang, Junchao.(2025).An Efficient Paillier Homomorphic Encryption Circuit With Optional CRT Acceleration for IoT.IEEE INTERNET OF THINGS JOURNAL,12(22),48146-48158.
MLA	Feng, Jundong,et al."An Efficient Paillier Homomorphic Encryption Circuit With Optional CRT Acceleration for IoT".IEEE INTERNET OF THINGS JOURNAL 12.22(2025):48146-48158.