AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models

doi:10.1145/3737286

CSpace

	AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models
	Li, Cangyuan 1,2; Chen, Chujie 2,3; Pan, Yudong 1; Xu, Wenjun 2,3; Liu, Yiqi 2,4; Chang, Kaiyan 2,5; Wang, Yujie 1; Wang, Mengdi 1; Li, Huawei 6,7; Han, Yinhe 1,8; Wang, Ying 1
	2025-11-01
发表期刊	ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
ISSN	1084-4309
卷号	30 期号:6 页码:21
摘要	Hardware description language (HDL) code designing is a critical component of the chip design process, requiring substantial engineering and time resources. Recent advancements in large language models (LLMs), such as GPT series, have shown promise in automating HDL code generation. However, current LLM-based approaches face significant challenges in meeting real-world hardware design requirements, particularly in handling complex designs and ensuring code correctness. Our evaluations reveal that the functional correctness rate of LLM-generated HDL code significantly decreases as design complexity increases. In this article, we propose the AutoSilicon framework, which aims to scale up the hardware design capability of LLMs. AutoSilicon incorporates an agent system, which (1) allows for the decomposition of large-scale, complex code design tasks into smaller, simpler tasks; (2) provides a compilation and simulation environment that enables LLMs to compile and test each piece of code it generates; and (3) introduces a series of optimization strategies. Experimental results demonstrate that AutoSilicon can scale hardware designs to projects with code equivalent to over 10,000 tokens. In terms of design quality, it further improves the syntax correctness rate and functional correctness rate compared with approaches that do not employ any extensions. For example, compared to directly generating HDL code using GPT-4-turbo, AutoSilicon enhances the syntax correctness rate by an average of 35.8% and improves functional correctness by an average of 35.6%.
关键词	Verilog code generation LLM agent verilog
DOI	10.1145/3737286
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:001616616200009
出版者	ASSOC COMPUTING MACHINERY
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/42962
专题	中国科学院计算技术研究所
通讯作者	Wang, Yujie; Han, Yinhe; Wang, Ying
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Res Ctr Intelligent Comp Syst, Beijing, Peoples R China 2.Univ Chinese Acad Sci, Beijing, Peoples R China 3.Univ Chinese Acad Sci, Hangzhou Inst Adv Study, Hangzhou, Peoples R China 4.Chinese Acad Sci, Inst Comp Technol, Beijing, Peoples R China 5.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing, Peoples R China 6.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processor, Beijing, Peoples R China 7.Peng Cheng Lab, Shenzhen, Peoples R China 8.Zhejiang Lab, Hangzhou, Peoples R China
推荐引用方式 GB/T 7714	Li, Cangyuan,Chen, Chujie,Pan, Yudong,et al. AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2025,30(6):21.
APA	Li, Cangyuan.,Chen, Chujie.,Pan, Yudong.,Xu, Wenjun.,Liu, Yiqi.,...&Wang, Ying.(2025).AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,30(6),21.
MLA	Li, Cangyuan,et al."AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 30.6(2025):21.