DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme

doi:10.1145/3773768

CSpace

	DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme
	Liu, Tianyu 1,2; Fan, Zhihua 1,2; Li, Wenming 1,2; Wang, Zhen 1,2; Qiu, Yuhang 1,2; Tang, Shengzhong 1,2; Wu, Haibin 1,2; Liu, Yanhuan 1,2; Ye, Xiaochun 1,2; Fan, Dongrui 1,2
	2025-12-01
发表期刊	ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
ISSN	1544-3566
卷号	22 期号:4 页码:26
摘要	Coarse-Grained Reconfigurable Architectures (CGRAs) have been regarded as promising spatial computing fabric for the ever-evolving algorithms in multiple domains. However, pure software scheduling cannot compensate for the deficiencies in over-serialization and load imbalancing of these pure static CGRA designs. To address the issues caused by limited hardware flexibility, an in-depth study on the balance between the software and hardware scheduling design of CGRA is needed to achieve more precise, accurate, and adaptive scheduling of dataflow. In this article, we propose DFGAS (DFG-Aware Scheduling), a dataflow-driven CGRA which provides a comprehensive scheduling approach that encompasses software prediction, runtime adaptive execution, and post-execution refinement. Prior to execution, the TimeStamp prediction algorithm, coupled with the inherent dataflow execution model, enables coarse-grained (block-level) prediction for prioritized transfer and computation on NoC and PEs. During execution, the execution of key dataflow graph (DFG) blocks and edges is accelerated by incorporating a dynamic and adaptive dataflow mechanism. It leverages hardware-software co-design to obtain a holistic view of the entire DFG and continuously self-adaptively optimizes the scheduling process. Furthermore, a complete workflow is implemented, supporting making refinements to the software DFG mapping results. DFGAS represents a scheduling scheme of CGRA that is worth exploring, achieving hardware-software co-design that balances energy efficiency and flexibility. Experiments show that DFGAS achieves 1.35x energy efficiency improvement over a dataflow-driven CGRA and 1.9x energy efficiency improvement over a state-of-the-art pure static CGRA.
关键词	CGRA hardware-software co-design network-on-chip
DOI	10.1145/3773768
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Theory & Methods
WOS记录号	WOS:001667494000010
出版者	ASSOC COMPUTING MACHINERY
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/42888
专题	中国科学院计算技术研究所
通讯作者	Fan, Zhihua; Li, Wenming
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing, Peoples R China 2.Univ Chinese Acad Sci, Sch Comp Sci & Technol, Beijing, Peoples R China
推荐引用方式 GB/T 7714	Liu, Tianyu,Fan, Zhihua,Li, Wenming,et al. DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme[J]. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION,2025,22(4):26.
APA	Liu, Tianyu.,Fan, Zhihua.,Li, Wenming.,Wang, Zhen.,Qiu, Yuhang.,...&Fan, Dongrui.(2025).DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme.ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION,22(4),26.
MLA	Liu, Tianyu,et al."DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme".ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 22.4(2025):26.