Institute of Computing Technology, Chinese Academy IR
| Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption | |
| Du, Yibo1,2; Wang, Ying1,2; Wang, Mengdi1,2; Li, Xiaowei3; Han, Yinhe1,2 | |
| 2026-02-01 | |
| 发表期刊 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
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| ISSN | 0278-0070 |
| 卷号 | 45期号:2页码:603-616 |
| 摘要 | fully homomorphic encryption (FHE) is a promising privacy-preserving technique that has drawn increasing attention from academia and industry. It allows computation directly on encrypted data without decryption. However, FHE incurs intensive computations. Chiplet-based designs integrate multiple processors, delivering high performance and thereby are embraced by computation-intensive FHE tasks. Despite the chiplet-based system with various processors, it is designed for unencrypted applications, falling short in handling FHE with unique ciphertext manipulations. One common approach to make it capable of FHE is developing a new FHE accelerator. However, this approach overlooks existing abundant resources already in the system and introduces a large area overhead. In this article, we propose Chiplever, a framework that empowers a non-FHE-tailored system to efficiently support FHE tasks via a hardware extension. Chiplever aims to leverage the existing resources already in the room for FHE tasks. To achieve this, 1) Chiplever introduces a hardware extension with an FHE unit providing efficient function support for FHE operators. 2) Chiplever proposes an FHE coordinator in the extension, which enables direct ciphertext transfer between the newly introduced extension and existing chiplets, achieving efficient integration of the extension. 3) Chiplever lowers the high-level homomorphic operations to primitive operators that can be matched by existing chiplets and constructs a fine-grained computation graph (CG). Based on this, Chiplever employs a task scheduling algorithm, which partitions the FHE task across the extension and existing chiplets to exploit the parallelism between them and reduce the ciphertext communication overheads. With these hardware and software optimizations, Chiplever achieves efficient FHE acceleration. Compared with prior FHE ASICs, Chiplever achieves $9.6{\times }$ - $15.9{\times }$ speedup and $6.2{\times }$ - $67.4{\times }$ throughput improvement on TFHE, while consuming only 18.8%-35.6% of the area overhead of dedicated FHE ASICs. |
| 关键词 | Hardware Chiplets Homomorphic encryption Polynomials Vectors Scheduling algorithms Noise Program processors Design automation Computational efficiency Chiplet fully homomorphic encryption (FHE) hardware-software co-design heterogeneous architecture |
| DOI | 10.1109/TCAD.2025.3583947 |
| 收录类别 | SCI |
| 语种 | 英语 |
| WOS研究方向 | Computer Science ; Engineering |
| WOS类目 | Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic |
| WOS记录号 | WOS:001667776300004 |
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| 引用统计 | |
| 文献类型 | 期刊论文 |
| 条目标识符 | http://119.78.100.204/handle/2XEOYT63/42836 |
| 专题 | 中国科学院计算技术研究所 |
| 通讯作者 | Wang, Ying; Han, Yinhe |
| 作者单位 | 1.Chinese Acad Sci, CICS, Inst Comp Technol, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Dept Comp Sci, Beijing 100190, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100190, Peoples R China |
| 推荐引用方式 GB/T 7714 | Du, Yibo,Wang, Ying,Wang, Mengdi,et al. Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2026,45(2):603-616. |
| APA | Du, Yibo,Wang, Ying,Wang, Mengdi,Li, Xiaowei,&Han, Yinhe.(2026).Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,45(2),603-616. |
| MLA | Du, Yibo,et al."Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 45.2(2026):603-616. |
| 条目包含的文件 | 条目无相关文件。 | |||||
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