JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits

doi:10.1109/TC.2025.3625822

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	JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits
	Fu, Rongliang 1; Zhou, Minglei 2; Chen, Siyan 3; Chen, Xinda 3; Huang, Junying 2; Ye, Xiaochun 2; Zhang, Zhimin 2; Ho, Tsung-Yi 1
	2026
发表期刊	IEEE TRANSACTIONS ON COMPUTERS
ISSN	0018-9340
卷号	75 期号:1 页码:290-304
摘要	Superconducting rapid single-flux-quantum (RSFQ) logic is a promising candidate for advancing future computing technologies due to its low-energy consumption and high-frequency capabilities. However, precise timing alignment is crucial for its physical design, posing significant challenges in length-matching placement and routing. This paper introduces JPnR, a physical design framework tailored for RSFQ circuits, featuring a clock-aware length-matching placer and a length-matching multi-terminal router. The placer simultaneously considers both clock distribution and timing constraints, distributing clock pulses heuristically and transforming the placement problem into a single-source shortest-path problem. This allows it to minimize vertical wirelength using dynamic programming and iteratively optimize placement via a barycenter-like reordering method. The router tackles challenges related to splitter placement and length-matching multi-terminal routing using a two-layer planar Manhattan routing model. Initial routing assigns tracks based on the left-edge algorithm to minimize routing width while employing the dogleg algorithm to resolve cycles in the vertical constraint graph. Length-matching is achieved via a splitter tree-based hierarchical approach with maximum-flow-based detour insertion. Finally, a PTL region expansion strategy is employed for unsatisfied connections. Experimental results on RSFQ benchmarks demonstrate the effectiveness and efficiency of JPnR.
关键词	Logic gates Routing Circuits Clocks Physical design Delays Logic Trees (botanical) Switches Layout Superconducting electronics single-flux-quantum placement routing length-matching clock-aware
DOI	10.1109/TC.2025.3625822
收录类别	SCI
语种	英语
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:001635821300001
出版者	IEEE COMPUTER SOC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/42834
专题	中国科学院计算技术研究所
通讯作者	Huang, Junying
作者单位	1.Chinese Univ Hong Kong, Dept Comp Sci & Engn, Hong Kong 999077, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing 100190, Peoples R China 3.ShanghaiTech Univ, Shanghai 201210, Peoples R China
推荐引用方式 GB/T 7714	Fu, Rongliang,Zhou, Minglei,Chen, Siyan,et al. JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits[J]. IEEE TRANSACTIONS ON COMPUTERS,2026,75(1):290-304.
APA	Fu, Rongliang.,Zhou, Minglei.,Chen, Siyan.,Chen, Xinda.,Huang, Junying.,...&Ho, Tsung-Yi.(2026).JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits.IEEE TRANSACTIONS ON COMPUTERS,75(1),290-304.
MLA	Fu, Rongliang,et al."JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits".IEEE TRANSACTIONS ON COMPUTERS 75.1(2026):290-304.