SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration

doi:10.1109/TCAD.2025.3546881

	SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration
	Xue, Runzhen 1,2; Yan, Mingyu 1,2; Han, Dengke 1,2; Xiao, Ziheng 1; Tang, Zhimin 1,2,3; Ye, Xiaochun 1,2; Fan, Dongrui 1,2
	2025-09-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	44 期号:9 页码:3490-3503
摘要	Heterogeneous graph neural networks (HGNNs) have expanded graph representation learning to heterogeneous graph fields. Recent studies have demonstrated their superior performance across various applications, including circuit representation, chip design automation, and placement optimization, often surpassing existing methods. However, GPUs often experience inefficiencies when executing HGNNs due to their unique and complex execution patterns. Compared to traditional graph neural networks (GNNs), these patterns further exacerbate irregularities in memory access. To tackle these challenges, recent studies have focused on developing domain-specific accelerators for HGNNs. Nonetheless, most of these efforts have concentrated on optimizing the datapath or scheduling data accesses, while largely overlooking the potential benefits that could be gained from leveraging the inherent properties of the semantic graph, such as its topology, layout, and generation. In this work, we focus on leveraging the properties of semantic graphs to enhance HGNN performance. First, we analyze the semantic graph build (SGB) stage and identify significant opportunities for data reuse during semantic graph generation. Next, we uncover the phenomenon of buffer thrashing during the graph feature processing (GFP) stage, revealing potential optimization opportunities in semantic graph layout. Furthermore, we propose a lightweight hardware accelerator frontend for HGNNs, called SiHGNN. This accelerator frontend incorporates a tree-based SGB for efficient semantic graph generation and features a novel Graph Restructurer for optimizing semantic graph layouts. Experimental results show that SiHGNN enables the state-ofthe-art HGNN accelerator to achieve an average performance improvement of 2.95x.
关键词	Semantics Layout Graph neural networks Optimization Vectors Graphics processing units Feature extraction Design automation Training Hardware acceleration Graph neural network (GNN) hardware accelerator heterogeneous graph neural network (HGNN) semantic graph
DOI	10.1109/TCAD.2025.3546881
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2022YFB4501400] ; National Natural Science Foundation of China[62202451] ; CAS Project for Young Scientists in Basic Research[YSBR-029] ; CAS Project for Youth Innovation Promotion Association
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:001563972400023
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/41741
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Yan, Mingyu
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100045, Peoples R China 2.Univ Chinese Acad Sci, Sch Comp Sci & Technol, Beijing 101408, Peoples R China 3.Shenzhen Univ Adv Technol, Fac Computil Microelect, Shenzhen 518107, Peoples R China
推荐引用方式 GB/T 7714	Xue, Runzhen,Yan, Mingyu,Han, Dengke,et al. SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2025,44(9):3490-3503.
APA	Xue, Runzhen.,Yan, Mingyu.,Han, Dengke.,Xiao, Ziheng.,Tang, Zhimin.,...&Fan, Dongrui.(2025).SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,44(9),3490-3503.
MLA	Xue, Runzhen,et al."SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 44.9(2025):3490-3503.