SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity

doi:10.1109/TCAD.2025.3553074

	SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity
	Jin, Pengwei 1,2,3; Fan, Zhe 3; Zhao, Yongwei ; Du, Zidong 1,4; Guo, Hongrui 1,2,3; Nan, Ziyuan 1,2,3; Hao, Yifan ; Li, Chongxiao 1,2,3; Ma, Tianyun 1,3,5; Zhang, Zhenxing 1,3,5; Li, Xiaqing 6; Li, Wei ; Hu, Xing 1,4; Guo, Qi ; Xu, Zhiwei 1,2; Chen, Tianshi 3
	2025-10-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	44 期号:10 页码:3962-3975
摘要	Due to the end of Moore's Law and Dennard Scaling, Domain-Specific Accelerators (DSAs) have come to a Cambrian explosion. Especially when advancing into the intelligent era, more and more DSAs are integrated into System-on-Chips (SoCs) as intellectual property (IP) blocks to provide high performance and efficiency. Currently, IPs usually expose IP-dependent hardware interfaces, requiring SoCs to manage them as isolated devices with software running on the host CPU. However, such software-managed heterogeneity in CPU-centric SoCs leads to low IP utilization. This inefficiency arises from the dependence on software optimization, coupled with the control and data exchange overheads. To improve IP utilization of heterogeneous SoCs, in this article, we rearchitect the SoC as a processor (i.e., SaaP) to orchestrate hardware heterogeneity. SaaP features an orchestration pipeline where DSAs are integrated as execution units and managed directly by the hardware pipeline to conceal the hardware heterogeneity from software. Moreover, SaaP redesigns the register file and data paths to implement an IP-level data-forwarding mechanism, avoiding the costly control and data exchange in the CPU-centric execution model. Block data dependence among different DSAs is carefully resolved to exploit mixed-level parallelism and inter-IP data exchange. SaaP abstracts tasks as mixed-scale instructions, where each instruction can be mapped to different IPs. Experimental results show that compared against Xavier on six fully software-optimized benchmarks from different domains, SaaP-rearchitected Xavier achieves a $2.08{\times }$ speedup, with an 8.21% area reduction and only 2.98% increase in power consumption.
关键词	IP networks Hardware Graphics processing units Central Processing Unit Programming Software Pipelines System-on-chip Process control Neural networks Hardware heterogeneity system architectures System-on-Chip (SoC)
DOI	10.1109/TCAD.2025.3553074
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2022YFB4501600] ; NSF of China[U22A2028] ; NSF of China[62222214] ; NSF of China[62341411] ; NSF of China[62102398] ; NSF of China[62102399] ; NSF of China[62302478] ; NSF of China[62302483] ; NSF of China[62302480] ; NSF of China[62302481] ; NSF of China[62372436] ; Strategic Priority Research Program of the Chinese Academy of Sciences[XDB0660200] ; Strategic Priority Research Program of the Chinese Academy of Sciences[XDB0660201] ; Strategic Priority Research Program of the Chinese Academy of Sciences[XDB0660202] ; CAS Project for Young Scientists in Basic Research[YSBR-029] ; Youth Innovation Promotion Association CAS
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:001577057000033
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/41689
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Du, Zidong
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100049, Peoples R China 3.Cambricon Technol, Beijing 100191, Peoples R China 4.Shanghai Innovat Ctr Processor Technol, Shanghai 200235, Peoples R China 5.Univ Sci & Technol China, Sch Comp Sci & Technol, Hefei 230027, Peoples R China 6.Beijing Jiaotong Univ, Dept Comp Sci & Technol, Beijing 100044, Peoples R China
推荐引用方式 GB/T 7714	Jin, Pengwei,Fan, Zhe,Zhao, Yongwei,et al. SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2025,44(10):3962-3975.
APA	Jin, Pengwei.,Fan, Zhe.,Zhao, Yongwei.,Du, Zidong.,Guo, Hongrui.,...&Chen, Tianshi.(2025).SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,44(10),3962-3975.
MLA	Jin, Pengwei,et al."SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 44.10(2025):3962-3975.