Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation

doi:10.1145/3760777

	Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation
	Chao, Zhiteng 1,2; Gu, Feng 1,2; Huang, Junying 1,2; Li, Wenjie 1; Ye, Jing 1,2,3; Li, Huawei 1,2,3; Li, Xiaowei 1,2,3
	2025-09-01
发表期刊	ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
ISSN	1084-4309
卷号	30 期号:5 页码:27
摘要	Gate-level fault simulation is essential for automatic test pattern generation (ATPG). The traditional event-driven simulation is time-consuming due to the large number of faults. While parallel fault simulation with GPGPUs shows promise, it faces reduced parallel efficiency on large circuits. This is mainly due to the increased space required to store fault values, limiting the number of faults that can be processed in parallel and preventing full utilization of the GPU's capabilities. In this study, we propose a memory-efficient fault machine implementation FMgpu based on a circular vector, which is tailored for GPU fault simulation with some sacrifices of time efficiency and a variable length limit. We also propose a fully adaptive parallel fault simulation framework based on the CPU-GPU heterogeneous system, which includes two stages on the GPU and performs CPU simulation at the same time. All parameters related to GPU memory optimization and workload balancing in the framework can be adjusted adaptively. The experimental results demonstrate that our method achieves better memory efficiency and speedup compared to the previous GPU fault simulation methods, a maximum speedup of 137.48x compared to the baseline open-source simulator with 32 threads, and a maximum speedup of 2.52x compared to a 32-thread commercial tool.
关键词	Heterogeneous memory-efficient adaptive
DOI	10.1145/3760777
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China (NSFC)[92373206] ; National Natural Science Foundation of China (NSFC)[92473203] ; Youth Innovation Promotion Association, CAS
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:001606095500009
出版者	ASSOC COMPUTING MACHINERY
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/41607
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Li, Wenjie; Li, Huawei
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing, Peoples R China 2.Univ Chinese Acad Sci, Sch Comp Sci & Technol, Beijing, Peoples R China 3.CASTEST Co Ltd, Beijing, Peoples R China
推荐引用方式 GB/T 7714	Chao, Zhiteng,Gu, Feng,Huang, Junying,et al. Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2025,30(5):27.
APA	Chao, Zhiteng.,Gu, Feng.,Huang, Junying.,Li, Wenjie.,Ye, Jing.,...&Li, Xiaowei.(2025).Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,30(5),27.
MLA	Chao, Zhiteng,et al."Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 30.5(2025):27.