Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators

doi:10.1109/TVLSI.2025.3526201

	Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators
	Xu, Sheng 1,2; Li, Chun 1; Luo, Le 1; Zhou, Wu 1; Yan, Liang 3; Chen, Xiaoming 3
	2025-01-15
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
页码	12
摘要	The integrated architecture that features both in-memory logic and host processors, or so-called "processing-in-memory" (PIM) architecture, is an emerging and promising solution to bridge the performance gap between the memory and host processors. In spite of the considerable potential of PIM, the workload offloading policy, which partitions the program and determines where code snippets are executed, is still a main challenge in PIM. In order to determine the best PIM offloading partitions, existing methods require in-depth program profiling to create the control flow graph (CFG) and then transform it into a graph-cut problem. These CFG-based solutions depend on detailed profiling of a crucial element, the execution time of basic blocks, to accurately assess the benefits of PIM offloading. The issue is that these execution times can change significantly in PIM, leading to inaccurate offloading decisions. To tackle this challenge, we present a novel PIM workload offloading framework called "RDPIM" for CPU-PIM graph processing accelerators, which systematically considers the variations in the execution time of basic blocks. By analyzing the relationship between data dependencies among workloads and the connectivity of input graphs, we identified three key features that can lead to variations in execution time. We developed a novel reuse distance (RD)-based model to predict the exact performance of basic blocks for optimal offloading decisions. We evaluate RDPIM using real-world graphs and compare it with some state-of-the-art PIM offloading approaches. Experiments have demonstrated that our method achieves an average speedup of 2x compared to CPU-only executions and up to 1.6x compared to state-of-the-art PIM offloading schemes.
关键词	Program processors Logic Codes Arrays Runtime Electronic mail Accuracy Very large scale integration Training Through-silicon vias Graph processing heterogenous systems processing-in-memory (PIM) reuse distance (RD) workload offloading
DOI	10.1109/TVLSI.2025.3526201
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[62102005] ; National Natural Science Foundation of China[62122076] ; National Natural Science Foundation of China[62488101] ; National Natural Science Foundation of China[62495104] ; University Synergy Innovation Program of Anhui Province[GXXT-2021-011] ; Key Research Program of Frontier Sciences, Chinese Academy of Sciences (CAS)[ZDBS-LY-JSC012] ; Open Research Fund of Anhui Engineering Research Center of Vehicle Display Integrated Systems[VDIS2023B01] ; Youth Innovation Promotion Association, CAS
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:001398757100001
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/40745
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Chen, Xiaoming
作者单位	1.Anhui Normal Univ, Sch Comp & Informat, Wuhu 241000, Anhui, Peoples R China 2.Inst Artificial Intelligence, Hefei Comprehens Natl Sci Ctr, Hefei 230088, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Xu, Sheng,Li, Chun,Luo, Le,et al. Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2025:12.
APA	Xu, Sheng,Li, Chun,Luo, Le,Zhou, Wu,Yan, Liang,&Chen, Xiaoming.(2025).Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,12.
MLA	Xu, Sheng,et al."Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2025):12.